Ferroelectric Memory Cell Layout With Gate-Defined Dielectric Films
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Solution Overview
Problem
Existing ferroelectric memory cell manufacturing methods face issues with mask misalignment leading to formation defects and increased size due to the need for separate processing of dielectric and ferroelectric films, resulting in larger semiconductor chips.
Innovation Solution
A manufacturing method where the ferroelectric films are processed after forming the control and memory gate electrodes, using these electrodes as masks to form the gate dielectric films, reducing the need for additional masks and allowing for closer spacing between gate electrodes, thereby miniaturizing the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the dielectric film and ferroelectric film are processed separately using different masks, then the formation defects are prevented, but the processing margin increases leading to larger device size
Solution Approach 1:
The patent combines the processing of dielectric film and ferroelectric film into a single mask step. The gate electrode pattern serves as a common mask for simultaneously defining both the dielectric film regions and ferroelectric film regions, eliminating the need for separate mask alignment steps and reducing the overall device footprint.
Solution Approach 2:
The gate electrode pattern performs multiple functions: it serves as both the functional gate electrode and as the mask pattern for defining the boundaries of both dielectric and ferroelectric films. This multi-functional approach eliminates the need for dedicated mask structures, thereby reducing device area.
2Reliability
If the distances between dielectric film, ferroelectric film, control gate electrode, and memory gate electrode are increased to secure processing margin, then mask misalignment is prevented, but the ferroelectric memory cell size increases
Solution Approach 1:
The patent merges the mask definition for dielectric films and ferroelectric films into a single gate electrode pattern. This unified approach eliminates cumulative mask alignment errors that would occur with multiple separate mask steps, allowing for tighter spacing between components without sacrificing alignment accuracy.
3Manufacturing precision
If separate masks are used for processing dielectric film and ferroelectric film, then formation defects are avoided, but the number of manufacturing steps increases
Solution Approach 1:
The patent combines multiple film processing operations into a single mask step using the gate electrode pattern. Both the dielectric film and ferroelectric film are defined simultaneously in one etching or deposition step, reducing the total number of manufacturing steps while maintaining precise film formation through the well-defined gate electrode boundaries.
Data Source
AI summary
A semiconductor device includes a ferroelectric memory cell, and the ferroelectric memory cell includes a select transistor and a memory transistor. A gate dielectric film of the select transistor includes a ferroelectric film, and a gate dielectric film of the memory transistor includes a ferroelectric film.