Ferroelectric Gate-All-Around Memory Structure for Low-Power Speed
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high performance and low power consumption, particularly in nonvolatile memory devices, where existing technologies struggle to integrate ferroelectric materials effectively for improved storage and operational efficiency.
Innovation Solution
A semiconductor device is designed using a ferroelectric material with a specific structure that includes a substrate, semiconductor patterns, gate electrodes, and ferroelectric layers, where the gate structure is formed on top, bottom, and side surfaces of the semiconductor patterns, enhancing integration density and gate controllability. The method involves forming a stack structure on a substrate, patterning semiconductor patterns, and creating a gate structure with a ferroelectric layer to improve memory cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional nonvolatile memory devices are used, then data storage capability is provided, but performance and power consumption are insufficient
Solution Approach 1:
The patent changes the material parameter by introducing a ferroelectric layer with specific dielectric properties into the memory device structure. This material parameter change enables nonvolatile data storage while improving operational speed and reducing power consumption compared to conventional volatile memory devices
Solution Approach 2:
The patent creates a composite structure by combining the ferroelectric layer with the gate dielectric layer and gate electrode. This composite material approach integrates the nonvolatile storage capability of ferroelectric materials with the functional requirements of memory device operation, achieving both high performance and low power consumption
2Reliability
If ferroelectric materials are integrated into memory devices, then nonvolatile storage capability is achieved, but integration density and gate controllability are insufficient
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate structures that wrap around semiconductor patterns. This dimensional change allows the gate electrode to contact the ferroelectric layer and semiconductor patterns from multiple directions (top, bottom, and side surfaces), significantly improving gate controllability and integration density while maintaining data retention
3Ease of operation
If gate structures are formed on multiple surfaces of semiconductor patterns, then gate controllability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the gate structure into distinct components: a gate dielectric layer, a ferroelectric layer, and a gate electrode. This segmentation allows each layer to be formed and controlled independently during fabrication, making the complex multi-surface gate structure manufacturable through sequential deposition and patterning processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a nonvolatile semiconductor memory device with enhanced integration density and gate controllability, improving operational speed and maintaining data even when power is interrupted, thus addressing the limitations of existing technologies.
Implementation Method 1
a ferroelectric layer between the gate dielectric layer and the gate electrode
Data Source
AI summary
A semiconductor device may include a substrate; semiconductor patterns that are stacked on the substrate, extend in a first direction parallel to a top surface of the substrate, and are spaced apart from each other; a gate electrode including horizontal portions, that extend in a second direction crossing the first direction, and a vertical portion, that is in contact with the horizontal portions and extends in a third direction perpendicular to the top surface of the substrate; a gate dielectric layer between the semiconductor patterns and the gate electrode; and a ferroelectric layer between the gate dielectric layer and the gate electrode. Each of the semiconductor patterns may include impurity regions and a channel region between the impurity regions, the vertical portion may be on a first side surface of the channel region, and the horizontal portions may be on a top and bottom surface of the channel region.