Negative-Capacitance Ferroelectric Memory Gate for Lower Voltage
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Solution Overview
Problem
As semiconductor devices integrate more densely, reducing heat generation through lower operation voltage and power consumption becomes crucial, but existing nonvolatile memory devices face challenges in effectively managing these factors due to the increasing complexity of their structures.
Innovation Solution
The integration of a ferroelectric layer with negative capacitance and a gate dielectric layer structure with positive capacitance, connected in series, allows for internal voltage amplification, enabling reduced gate voltage application and decreased power consumption in nonvolatile memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration of semiconductor devices is increased, then productivity and device density are improved, but heat generation increases and operation voltage must be reduced
Solution Approach 1:
The patent introduces a ferroelectric layer that exhibits negative capacitance characteristics, fundamentally changing the electrical parameters of the gate dielectric system. This allows the gate voltage to be reduced while maintaining effective channel control, thereby reducing power consumption and heat generation in high-density integrated devices
2Use of energy by stationary object
If operation voltage is reduced to reduce power consumption, then heat generation is reduced, but the ability to withstand voltage and proper dissipation becomes challenging
Solution Approach 1:
The ferroelectric layer acts as an intermediary between the gate electrode and the channel, providing voltage amplification through its negative capacitance effect. This mediator enables the gate to exert stronger control over the channel at lower applied voltages, improving both power efficiency and voltage control reliability
Solution Approach 2:
By incorporating the ferroelectric layer with negative capacitance, the electrical parameters of the gate dielectric system are fundamentally altered, enabling enhanced voltage control and improved reliability at reduced operation voltages
3Use of energy by stationary object
If a ferroelectric layer with negative capacitance is integrated with a gate dielectric layer structure with positive capacitance, then gate voltage is reduced and power consumption decreases, but device structure complexity increases
Solution Approach 1:
The gate dielectric system is segmented into distinct functional layers: a charge tunneling layer, a charge trap layer, a charge barrier layer, and a ferroelectric layer. This segmentation allows each layer to perform its specific function independently, simplifying the overall design and fabrication process despite the increased number of layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the gate voltage required for operation, leading to lower power consumption and improved heat dissipation in nonvolatile memory devices, enhancing their performance and efficiency.
Implementation Method 1
The ferroelectric layer has a negative capacitance
Implementation Method 2
The gate dielectric layer structure has a positive capacitance
Implementation Method 3
a charge tunneling layer, a charge trap layer and a charge barrier layer as a gate dielectric layer structure
Data Source
AI summary
A nonvolatile memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a gate dielectric layer structure disposed on the channel layer, a ferroelectric layer disposed on the gate dielectric layer structure, and a gate electrode layer disposed on the ferroelectric layer. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The gate dielectric layer structure includes a charge tunneling layer, a charge trap layer and a charge barrier layer disposed on the channel layer.