Ferroelectric Memory Device with Graded Composition Layer
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in maintaining reliable operation and data storage due to issues like trap defects and oxygen vacancies in ferroelectric layers, which affect the endurance and fatigue performance of memory cells.
Innovation Solution
Incorporating a ferroelectric layer with specific species such as nitrogen or fluorine, which have a valence of 5 or 7, between the channel layer and conductive lines to eliminate traps, block defects, and occupy oxygen vacancies, thereby enhancing the intrinsic fatigue performance and endurance of the ferroelectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but trap defects and oxygen vacancies in ferroelectric layers increase, affecting endurance and fatigue performance
Solution Approach 1:
The patent applies local quality by introducing a graded composition ferroelectric layer where the ratio of first atoms to second atoms varies through the thickness of the layer. This creates different local regions with optimized properties: regions closer to the channel layer have compositions that reduce trap defects and oxygen vacancies, while other regions maintain high polarization. This local variation in composition allows the structure to simultaneously achieve high integration density and improved reliability by addressing defect formation in specific critical regions.
Solution Approach 2:
The patent employs parameter changes by systematically varying the chemical composition parameters of the ferroelectric layer. The ratio of first atoms (e.g., Hf, Zr) to second atoms (e.g., Ti, Si, O) is changed as a function of depth through the layer, creating a compositional gradient. This parameter variation optimizes the balance between polarization strength and defect reduction, enabling the ferroelectric layer to maintain reliable operation at reduced feature sizes while preserving endurance and fatigue performance.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but interdiffusion of oxygen, hydrogen, and vacancies increases, reducing reliability
Solution Approach 1:
The graded composition ferroelectric layer creates local regions with different atomic ratios that are specifically designed to resist interdiffusion. Regions adjacent to the channel layer have compositions that act as diffusion barriers, while other regions maintain electrical functionality. This local differentiation in composition allows the structure to prevent harmful interdiffusion of oxygen, hydrogen, and vacancies while maintaining high integration density through scaled-down feature sizes.
Solution Approach 2:
The patent utilizes composite material principles by creating a ferroelectric layer with non-uniform composition - essentially a composite of different stoichiometric regions within a single continuous layer. The variation in first atom to second atom ratios creates distinct compositional zones that function together: some zones provide diffusion barrier properties while others provide piezoelectric and ferroelectric functionality. This composite approach enables simultaneous achievement of high integration density and resistance to interdiffusion harmful effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability and endurance of ferroelectric memory cells by reducing interdiffusion of oxygen, hydrogen, and vacancies, making it easier to read and write digital values with reduced error, thus enhancing the overall performance of the memory device.
Implementation Method 1
Incorporating a ferroelectric layer with specific species such as nitrogen or fluorine, which have a valence of 5 or 7, between the channel layer and conductive lines to eliminate traps, block defects, and occupy oxygen vacancies
Implementation Method 2
This approach improves the reliability and endurance of ferroelectric memory cells by reducing interdiffusion of oxygen, hydrogen, and vacancies
Data Source
AI summary
A memory cell includes a transistor over a semiconductor substrate. The transistor includes a ferroelectric layer arranged along a sidewall of a word line. The ferroelectric layer includes a species with valence of 5, valence of 7, or a combination thereof. An oxide semiconductor layer is electrically coupled to a source line and a bit line. The ferroelectric layer is disposed between the oxide semiconductor layer and the word line.