Ferroelectric Memory Stack Structure for Uniform Grain Size
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Solution Overview
Problem
The miniaturization of ferroelectric layers in semiconductor devices leads to variations in grain size, affecting memory unit parameters such as memory window, endurance, and remnant polarization, resulting in inconsistent electrical performance and reliability among semiconductor devices.
Innovation Solution
A semiconductor structure with a plurality of thin ferroelectric layers stacked alternately with thin metal layers, where the metal layers restrict the grain size of the ferroelectric materials, ensuring consistent grain size and performance across devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If ferroelectric layers are miniaturized to reduce device size, then device scaling is achieved, but grain size variations increase causing inconsistent electrical performance
Solution Approach 1:
The patent divides the ferroelectric layer into multiple thin ferroelectric sub-layers separated by metal interlayer. This segmentation restricts grain growth within each thin sub-layer, ensuring uniform grain size even when the overall device is miniaturized, thus resolving the contradiction between device scaling and grain size consistency
Solution Approach 2:
The patent introduces a vertical stacking dimension with multiple thin ferroelectric layers separated by metal layers. This dimensional approach allows each thin layer to maintain uniform grain size while achieving overall device miniaturization through vertical integration rather than lateral scaling
2Volume of moving object
If thin ferroelectric layers are used to achieve miniaturization, then device size is reduced, but electrical performance consistency deteriorates due to grain size variations
Solution Approach 1:
By segmenting the ferroelectric layer into multiple thin sub-layers with metal interlayers, the patent ensures that each sub-layer develops uniform grain structure. This segmentation prevents grain size variations that would otherwise occur in miniaturized single-layer structures, thereby maintaining electrical performance consistency
Solution Approach 2:
The patent changes the structural parameter from a single thick ferroelectric layer to multiple thin layers with specific thickness ratios. This parameter change ensures that each thin layer maintains uniform grain size and consistent electrical properties, resolving the reliability issue in miniaturized devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The alternating deposition of ferroelectric and metal layers maintains uniform grain size, enhancing the electrical performance and reliability of semiconductor devices by reducing grain size variations, thereby improving consistency across multiple memory units.
Implementation Method 1
the metal layers restrict the grain size of the ferroelectric materials, ensuring consistent grain size and performance across devices
Implementation Method 2
The alternating deposition of ferroelectric and metal layers maintains uniform grain size
Data Source
AI summary
A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a substrate having a first surface, a first conductive region and a second conductive region at the first surface, wherein the first conductive region is apart from the second conductive region, a gate feature, wherein a top surface of the gate feature is above the first conductive region, a stack unit coupled to the first conductive region, wherein the stack unit includes a plurality of ferroelectric layers stacking with a plurality of metal layers, wherein each of the plurality of ferroelectric layers separates adjacent two metal layers.