Ferroelectric Memory Cell With Hollow Channel Transistor
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Solution Overview
Problem
Existing memory cell technologies face challenges in maintaining non-volatile data storage due to the reversible nature of ferroelectric capacitors, where reading memory states can inadvertently rewrite them, and there is a need for efficient methods to form arrays of memory cells with capacitors and transistors that can reliably store multiple states without data loss.
Innovation Solution
The formation of memory cells comprising a capacitor and a transistor, with rows of access lines and columns of digit lines, using methods that include the creation of capacitor openings and access transistors within an array, employing ferroelectric materials for non-volatile storage and hollow channel transistors to prevent data loss during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If ferroelectric capacitors are used for non-volatile storage, then data retention capability is improved, but reading memory states can inadvertently rewrite them due to reversible polarization
Solution Approach 1:
A tunnel barrier layer is introduced as an intermediary between the ferroelectric capacitor and the substrate. This tunnel barrier prevents charge leakage and eliminates the need for read-disturb rewrite operations, allowing non-volatile memory to be read without inadvertently rewriting the data. The tunnel barrier acts as a mediator that enables reliable charge storage while preventing the harmful side effect of read-induced polarization reversal.
2Ease of manufacture
If conventional memory cell structures are used, then manufacturing processes are simpler, but maintaining non-volatile storage without data loss during reads is difficult
Solution Approach 1:
The memory cell employs a composite capacitor structure combining multiple materials: a ferroelectric layer (Pb(Zr,Ti)O3 or Pb1-xLaxZr1-yTiyO3) for non-volatile storage, a tunnel barrier layer (oxide material) for charge retention, and electrode materials (Pt, Ru, Ir, or their alloys). This composite structure integrates the benefits of each material to achieve both non-volatile storage and read stability while maintaining compatibility with existing semiconductor manufacturing processes.
3Ease of manufacture
If access transistors are formed with standard processes, then manufacturing is easier, but hollow channel transistors are needed to prevent data loss during read operations
Solution Approach 1:
The access transistor is designed with a hollow channel structure where the channel region contains a void or low-dielectric material. This local structural modification in the transistor channel prevents charge leakage paths that would otherwise cause data loss during read operations. The hollow channel provides electrical isolation while maintaining the transistor's switching function, enabling reliable non-volatile memory operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable non-volatile data storage by using ferroelectric materials to maintain distinct memory states and hollow channel transistors to prevent data loss during read operations, enhancing the stability and efficiency of memory cell arrays.
Implementation Method 1
One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell.
Implementation Method 2
A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material.
Data Source
AI summary
A method of forming an array of capacitors and access transistors there-above comprises forming access transistor trenches partially into insulative material. The trenches individually comprise longitudinally-spaced masked portions and longitudinally-spaced openings in the trenches longitudinally between the masked portions. The trench openings have walls therein extending longitudinally in and along the individual trench openings against laterally-opposing sides of the trenches. At least some of the insulative material that is under the trench openings is removed through bases of the trench openings between the walls and the masked portions to form individual capacitor openings in the insulative material that is lower than the walls. Individual capacitors are formed in the individual capacitor openings. A line of access transistors is formed in the individual trenches. The line of access transistors electrically couples to the individual capacitors that are along that line. Other aspects, including structure independent of method, are disclosed.