Ferroelectric Memory Cell Lamination for Low-Voltage HZO Operation
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Solution Overview
Problem
Existing ferroelectric memory cells face challenges in reducing the operating voltage due to poor crystallinity of HZO films, leading to difficulties in achieving low-voltage operations.
Innovation Solution
A semiconductor device with a ferroelectric memory cell structure that includes a laminated body of three or more ferroelectric layers, separated by impurity particles, and a paraelectric film, enhancing crystallinity through two-dimensional crystal growth during a heat treatment process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing HZO film structure is used, then ferroelectric memory cell structure is simple, but operating voltage cannot be reduced
Solution Approach 1:
The ferroelectric film is divided into multiple thin layers (first, second, and third ferroelectric layers) with impurity particles positioned between them. This segmentation allows each layer to be optimized for specific functions, enabling reduced operating voltage while maintaining overall film performance through distributed crystallinity enhancement.
Solution Approach 2:
Impurity particles are introduced as intermediary elements between the ferroelectric layers. These particles serve as nucleation sites that promote two-dimensional crystal growth and enhance interfacial crystallinity, thereby reducing the operating voltage without requiring complete restructuring of the ferroelectric film architecture.
2Use of energy by moving object
If HZO film crystallinity is poor, then manufacturing process is simple, but operating voltage reduction is difficult
Solution Approach 1:
Impurity particles are positioned between the ferroelectric layers during the formation process, before the final heat treatment. This preliminary placement ensures that the particles serve as pre-positioned nucleation sites, guiding the subsequent two-dimensional crystal growth and ensuring high crystallinity without requiring complex post-processing adjustments.
Solution Approach 2:
The patent changes the physical and chemical parameters of the ferroelectric film by introducing impurity particles and performing heat treatment at specific temperatures. This induces a phase transformation that enhances crystallinity and enables reduced operating voltage, transforming the material properties through controlled parameter adjustment rather than complex manufacturing steps.
3Reliability
If three or more ferroelectric layers are laminated, then crystallinity is improved, but device structure becomes complex
Solution Approach 1:
The patent applies local quality enhancement by positioning impurity particles specifically at the interfaces between ferroelectric layers. This localized treatment improves crystallinity at critical interfaces without requiring complex overall structural changes, maintaining manufacturing feasibility while enhancing reliability through targeted crystallinity improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved crystallinity allows the ferroelectric memory cell to operate at reduced voltages of 4V or less, reducing power consumption and enabling efficient write and erase operations without modulating the power supply voltage.
Implementation Method 1
In the heat treatment step, each of the amorphous layers is crystallized in a horizontal direction to form a laminated film of ferroelectric
Implementation Method 2
discretely providing impurity particles on the surface of the amorphous layer
Data Source
AI summary
Enhancing the performance of semiconductor devices by reducing the operating voltage of a ferroelectric memory equipped with a ferroelectric film. On a semiconductor substrate, forming a laminated body including a paraelectric film, which is an insulating film, and the ferroelectric film made of three or more layers of ferroelectric layers to on the insulating film, and forming a metal film and a gate electrode on the ferroelectric film. By discretely placing impurity particles between the ferroelectric layers that are in contact with each other, the crystallinity of the ferroelectric film is enhanced.