Ferroelectric Memory Stacking with IDVs for CMOS Thermal Isolation
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Solution Overview
Problem
Thermal tolerance of CMOS devices limits the material selection of ferroelectric memories, and CMOS devices suffer from low reliability due to low stress tolerance to deformation of ferroelectric memories under operation.
Innovation Solution
The semiconductor structure involves separately manufacturing wafers with CMOS devices and ferroelectric memories and connecting them via inter die vias (IDVs), allowing the ferroelectric memories to be processed at higher temperatures without affecting the CMOS devices, and incorporating cavities beneath the ferroelectric layers to alleviate stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ferroelectric memories are manufactured separately from CMOS devices, then material selection flexibility is improved, but device complexity increases
Solution Approach 1:
The patent divides the manufacturing process into separate segments: CMOS devices are manufactured on a first wafer while ferroelectric memories are manufactured on a second wafer independently. This allows each component to be optimized separately with appropriate material selections, then the wafers are bonded together through wafer-level bonding to form the final integrated device.
2Manufacturing precision
If high temperature processing is used for ferroelectric memories, then ferroelectric material quality is improved, but CMOS device reliability deteriorates
Solution Approach 1:
The patent separates the thermal processing stages by manufacturing CMOS and ferroelectric components on different wafers. The ferroelectric wafer can undergo high temperature processing (e.g., annealing at 600-800°C) to achieve optimal material quality, while the CMOS wafer is processed at lower temperatures appropriate for standard CMOS fabrication. After independent processing, the wafers are bonded together, allowing each component to achieve its optimal processing conditions without compromising the other.
3Adaptability or versatility
If ferroelectric memories are integrated with CMOS devices, then device functionality is improved, but stress tolerance deteriorates
Solution Approach 1:
The patent manufactures CMOS devices and ferroelectric memories on separate wafers that are subsequently bonded together. This segmentation allows the ferroelectric wafer to be designed with appropriate stress management features (such as relaxed substrate constraints or compliant layers) that would be difficult to implement in a fully integrated process, while maintaining the functional integration benefits of combining both device types in a single package.
Data Source
AI summary
A semiconductor structure includes a first die, a second die, and an inter die via (IDV). The first die includes an interconnection structure and a CMOS device electrically connected to the interconnection structure. The second die includes a memory element including a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein a peripheral region of the ferroelectric layer is exposed by and surrounding the second electrode from a top view perspective. The IDV electrically connects the interconnection structure of the first die to the memory element of the second die.