3D Ferroelectric Memory Tiers for Leakage Isolation
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits has increased complexity in processing and manufacturing, particularly for 3D memory devices, where existing technologies face challenges in achieving high memory cell density and reducing leakage current between vertically stacked memory cells.
Innovation Solution
A 3D memory device design featuring a first tier with a plurality of memory cells and a second tier stacked over the first, with a dielectric material between them to reduce leakage current, and a ferroelectric material used in the gate structures to enhance memory cell density, allowing for easy modification and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically to increase density, then memory cell density increases, but leakage current between vertically neighboring memory cells increases
Solution Approach 1:
A dielectric material is introduced as an intermediary layer between vertically stacked memory cells. This dielectric material acts as a mediator that blocks electrical leakage while allowing the vertical stacking architecture to maintain high memory cell density. The dielectric material is positioned at the interface between tiers, preventing direct electrical contact between adjacent memory cells while preserving the compact 3D structure.
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency increases and costs decrease, but processing and manufacturing complexity increases
Solution Approach 1:
The memory device is segmented into multiple tiers with distinct functional regions. Each tier contains memory cells separated by dielectric materials, creating modular units that can be manufactured and assembled systematically. This segmentation allows complex 3D memory structures to be built from simpler repeating units, reducing overall manufacturing complexity while maintaining high functional density.
3Object-generated harmful factors
If dielectric material is added between memory cell tiers to reduce leakage, then leakage current decreases, but device structure becomes more complex
Solution Approach 1:
The dielectric material serves multiple functions simultaneously: it acts as an electrical insulator to block leakage current between tiers, provides structural support for the stacked architecture, and defines the boundaries between memory cell tiers. By combining multiple functions into a single material layer, the design reduces overall structural complexity while effectively addressing leakage current issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases memory cell density and improves device performance by reducing leakage current and facilitating miniaturization, while being compatible with existing semiconductor manufacturing processes.
Implementation Method 1
a dielectric material (e.g., isolation structure) is disposed between the first and second memory cells to reduce or eliminate the leakage current between two vertically neighboring memory cells
Implementation Method 2
a ferroelectric material used in the gate structures to enhance memory cell density
Data Source
AI summary
Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.