Ferroelectric Memory Cell Readout for Leakage-Limited Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ferroelectric memory cells face challenges with leakage currents that alter stored information over time, limiting retention time and preventing their adoption for non-volatile data storage, especially in small-scaled memory elements with low read currents and high leakage current densities.
Innovation Solution
The integration of a read transistor and a select transistor within a memory cell to amplify read signals and control electrical potential, along with a third circuit element such as a transistor, resistor, or diode, to manage leakage currents and maintain data integrity during read and write operations, allowing for non-destructive readout and improved memory cell design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If small-scaled memory elements are used to increase memory density, then memory density is improved, but leakage current density increases and read current decreases
Solution Approach 1:
The memory cell is segmented into multiple functional components: a first transistor for sensing, a second transistor for controlling electrical potential, and a capacitor for storing data. This segmentation allows each component to address specific issues - the first transistor amplifies weak read signals from small-scaled capacitors, while the second transistor manages leakage currents, enabling high-density storage without sacrificing reliability
Solution Approach 2:
The second transistor acts as an intermediary between the capacitor and the external circuit, controlling the electrical potential at the connection node. This intermediary function prevents leakage currents from directly affecting the stored charge, thereby maintaining data integrity in small-scaled memory elements where leakage is more pronounced
2Reliability
If read transistor is added to amplify read signals, then read operation reliability is improved, but device complexity increases
Solution Approach 1:
The first transistor serves multiple functions: it acts as a sensing element to detect the polarization state of the capacitor, functions as an amplifier to boost weak read signals, and participates in write operations by controlling charge transfer. This multi-functionality improves read reliability without proportionally increasing device complexity
Solution Approach 2:
The sensing and amplification functions are merged into a single transistor structure, eliminating the need for separate sensing and amplification circuits. This integration approach maintains compact cell design while achieving reliable read operations in small-scaled memory elements
3Reliability
If third circuit element is added to control electrical potential and manage leakage currents, then data integrity is improved, but device complexity increases
Solution Approach 1:
The second transistor serves as an intermediary control element that manages the electrical potential at the capacitor connection node. By controlling this potential, it prevents leakage currents from discharging the capacitor, thereby preserving data integrity without requiring complex leakage compensation circuits
Solution Approach 2:
The second transistor enables the memory cell to self-manage its electrical potential and counteract leakage effects through controlled charge redistribution. This self-service mechanism maintains data integrity passively without requiring external intervention or complex control logic
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables reliable sensing of polarization states in small-scaled capacitors with low switching charge or read currents, preventing data loss due to leakage currents and enhancing memory cell retention time without increasing the effective coercive voltage, thus optimizing memory density and read operation efficiency.
Implementation Method 1
Switching is caused by applying an electrical field via a voltage between the transistor gate and transistor channel. Specifically, for n-channel transistors, ferroelectric switching after applying a sufficiently high positive voltage pulse causes a shift of the threshold voltage to lower or more negative values
Implementation Method 2
such sensing is performed by either charging or discharging a bit line which is connected to the Source or Drain terminal of the FeFET and sensing the voltage change at the bit line after a certain time by sensing the current flow through the FeFET by adoption of a suitable sense amplifier (SA)
Data Source
AI summary
One example provides a memory cell including a node, and a layer stack including a first electrode, a second electrode connected to the node, and a polarizable material layer disposed between the first and second electrodes and having at least two polarization states. A first transistor includes a source, a drain, and a gate terminal, with the gate terminal connected to the node. A selector element includes at least a first terminal and a second terminal, with the second terminal connected to the node.