Ferroelectric Memory Line Asymmetry for Wider Memory Windows
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Solution Overview
Problem
Existing ferroelectric memory devices face challenges with narrow memory windows and limited switching performance due to symmetric source and bit line structures, which affect their operational efficiency and reliability.
Innovation Solution
The implementation of asymmetric source and bit line structures with a protruding portion of the bit line extending over the dielectric layer, laterally separated by an etch-stop layer, enhances the memory window and switching performance by increasing the fringing electric field and disparity in ferroelectric polarization within the channel layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If symmetric source and bit line structures are used, then manufacturing simplicity is maintained, but memory window width is narrow
Solution Approach 1:
The patent applies asymmetry by configuring the bit line structure to have a protruding portion that extends over the dielectric layer, while the source line remains symmetric with respect to the channel layer. This asymmetric configuration creates different fringing electric field distributions between the bit line and source line, thereby widening the memory window of the ferroelectric memory device without significantly complicating the manufacturing process
2Reliability
If asymmetric line structures with protruding portions are implemented, then switching performance is improved, but manufacturing complexity increases
Solution Approach 1:
The bit line structure is segmented into a main body portion and a protruding portion. The protruding portion is formed by extending the bit line electrode over the dielectric layer in a specific region, creating distinct functional zones that enhance switching performance while allowing standard fabrication processes to be applied to each segment
3Manufacturing precision
If etch-stop layer is used for lateral separation, then ferroelectric polarization disparity is increased, but device structure complexity increases
Solution Approach 1:
An etch-stop layer is introduced as an intermediary between the dielectric layer and the channel layer, positioned laterally between the source line and bit line structures. This etch-stop layer serves as a mediator that enhances the lateral separation effect, thereby increasing the disparity in ferroelectric polarization induced by the asymmetric line structures without requiring complex multi-layer configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration widens the memory window and improves read speed, enabling more efficient switching and increased reliability in ferroelectric memory devices, suitable for high-density applications.
Implementation Method 1
increasing the fringing electric field and disparity in ferroelectric polarization within the channel layer
Implementation Method 2
disparity in ferroelectric polarization within the channel layer
Data Source
AI summary
A semiconductor device includes a word line (WL) structure. The semiconductor device includes a ferroelectric layer over the WL structure. The semiconductor device includes a channel layer over the ferroelectric layer. The semiconductor device includes a source line (SL) structure over the channel layer. The semiconductor device includes a bit line (BL) structure over the channel layer. The BL structure includes a portion that laterally extends toward the SL structure. The semiconductor device further includes a dielectric layer laterally interposed between the SL structure and the BL structure.