Ferroelectric Multi-Channel Memory Structure for Multi-Bit Storage
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Solution Overview
Problem
Existing semiconductor devices face challenges in integrating ferroelectric materials effectively to enhance memory elements, leading to limitations in integration and electrical characteristics.
Innovation Solution
A semiconductor device design incorporating a substrate with a gate electrode and multiple channel layers surrounded by dielectric layers made of ferroelectric or anti-ferroelectric materials, each with varying coercive voltages, allowing for a multi-bridge channel FET structure that enables multi-level cell storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ferroelectric materials are integrated into memory elements to enhance storage capabilities, then multi-bit storage is enabled, but device complexity increases due to the need for multiple dielectric layers with different coercive voltages
Solution Approach 1:
The memory element is segmented into multiple channel layers (first, second, and third channel layers) with corresponding dielectric layers, where each layer pair can independently store one bit of data. This segmentation enables multi-bit storage capacity while maintaining manageable structural complexity through modular design
Solution Approach 2:
Different dielectric layers are assigned different coercive voltages (first dielectric layer with first coercive voltage, second with second, third with third), creating local quality variations that enable independent control of each storage bit. This allows selective programming and reading of individual bits within the multi-level cell structure
2Area of stationary object
If multiple channel layers are stacked vertically to increase integration density, then area efficiency improves, but manufacturing precision requirements increase due to the need for precise alignment and spacing
Solution Approach 1:
The invention transitions from planar single-layer memory structure to vertical multi-layer stacking, utilizing the third dimension (height) to increase storage capacity. Multiple channel layers are stacked vertically with dielectric layers in between, enabling higher integration density without increasing the device footprint area
Solution Approach 2:
The structure employs a nested configuration where dielectric layers are positioned between and surrounding portions of the channel layers, with gate electrodes wrapping around the channel-dielectric assemblies. This nested arrangement maximizes space utilization and maintains compact geometry while achieving multi-level storage
3Quantity of substance
If dielectric layers with different coercive voltages are used to enable multi-level cell storage, then storage density increases, but electrical characteristics become more difficult to control
Solution Approach 1:
The invention systematically varies the coercive voltage parameter across different dielectric layers (first coercive voltage for first dielectric layer, second for second, third for third), creating a graded parameter structure. This enables distinct voltage thresholds for programming different bits, improving electrical control reliability while maintaining high storage density through multi-level cell operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves integration and electrical characteristics, enabling multi-bit storage capabilities by utilizing the varying coercive voltages of the dielectric layers to implement a multilevel cell structure.
Implementation Method 1
a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers including at least one of a ferroelectric material or an anti-ferroelectric material, and each of the plurality of dielectric layers having a different coercive voltage
Implementation Method 2
the plurality of dielectric layers including at least one of a ferroelectric material or an anti-ferroelectric material
Data Source
AI summary
A semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode on the substrate and extending in a second direction, and a plurality of channel layers on the active region. The plurality of channel layers are spaced apart from each other in a third direction perpendicular to an upper surface of the substrate. The device includes a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers include at least one of a ferroelectric material or an anti-ferroelectric material, and each of the plurality of dielectric layers has a different coercive voltage. The device includes source/drain regions in recess regions in which the active region is recessed, the source/drain regions are on both sides of the gate electrode, and the source/drain regions are in contact with the plurality of channel layers.