Ferroelectric Memory Structure Without Interfacial Insulation Layer
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Solution Overview
Problem
Ferroelectric memory devices face issues with non-uniform polarization switching and reliability due to the use of amorphous interfacial insulation layers, which lead to voltage drop and trap site formation, resulting in degraded performance and endurance.
Innovation Solution
The introduction of an epitaxial channel layer with low oxygen reactivity, eliminating the need for an interfacial insulation layer, and the use of a threshold switching layer to control voltage, stabilizing ferroelectric characteristics and improving polarization switching uniformity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an amorphous interfacial insulation layer is used between the channel layer and ferroelectric layer, then the interface is isolated, but voltage drop occurs and trap sites form, degrading polarization switching uniformity and reliability
Solution Approach 1:
The patent removes the amorphous interfacial insulation layer from the structure. By extracting this problematic layer, the invention eliminates the source of voltage drop and trap site formation, allowing direct contact between the channel layer and ferroelectric layer to achieve better electrical characteristics and polarization switching uniformity
Solution Approach 2:
The patent employs a composite structure where a crystalline channel layer (such as silicon carbide or silicon germanium) directly interfaces with the ferroelectric layer. This composite material approach creates a stable, low-defect interface that prevents trap site formation while maintaining proper electrical isolation through the crystalline structure itself
2Reliability
If an amorphous interfacial insulation layer is used, then interface isolation is achieved, but trap sites form leading to leakage currents
Solution Approach 1:
The patent removes the amorphous interfacial insulation layer that generates trap sites. By extracting this layer, the invention eliminates the harmful factor of leakage current while maintaining interface isolation through the crystalline channel layer structure
Solution Approach 2:
The patent creates an inert interface environment by using chemically stable crystalline materials (such as silicon carbide or silicon germanium) that resist oxidation and trap site formation. This inert crystalline interface prevents the generation of leakage currents while maintaining proper electrical characteristics
3Reliability
If a threshold switching layer is added to control voltage, then polarization switching uniformity improves, but device structure becomes more complex
Solution Approach 1:
The patent makes the channel layer multi-functional by designing it to simultaneously serve as both the conductive channel and the interfacial insulation layer. This universal approach eliminates the need for separate threshold switching layers while maintaining voltage control and ferroelectric stability
Solution Approach 2:
The patent merges the functions of the channel layer and interfacial insulation layer into a single crystalline structure. By combining these functions, the invention simplifies the device structure while achieving proper voltage control and stable ferroelectric characteristics through the crystalline material properties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the uniformity and reliability of polarization switching operations, reduces the need for increased operation voltages, and prevents leakage currents, thereby improving the durability and performance of ferroelectric memory devices.
Implementation Method 1
The introduction of an epitaxial channel layer with low oxygen reactivity, eliminating the need for an interfacial insulation layer
Implementation Method 2
the different potential polarization orientations may induce different types of charge into a channel region of the transistor. As a result, a channel resistance of the transistor can be measured to identify the stored remanent polarization
Data Source
AI summary
A ferroelectric memory device includes a semiconductor substrate, a fin structure disposed on the semiconductor substrate and having a trench, the trench having a bottom surface and a sidewall surface; a ferroelectric layer disposed on the bottom surface and the sidewall surface of the trench; a plurality of resistor layers stacked vertically in the trench, each resistor layer of the plurality of resistor layers having a different electrical resistance; and a gate electrode layer electrically connected to the each resistor layer in the plurality of resistor layers. The plurality of resistor layers are disposed between the gate electrode layer and the ferroelectric layer.