Ferroelectric Memory Power Isolation for Noise Reduction
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Solution Overview
Problem
Ferroelectric random access memories (FRAMs) face challenges in maintaining signal integrity during write and write-back operations due to high electrical noise, which can corrupt data, and existing technologies do not effectively isolate the memory from power supply during these cycles to mitigate this issue.
Innovation Solution
The implementation of a method that electrically disconnects the ferroelectric memory from the power supply during write and write-back cycles and uses capacitors to provide energy, ensuring that the power supply is only reconnected after the cycle is complete, thereby isolating the memory from noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the ferroelectric memory is connected to the power supply during write and write-back cycles, then the memory can receive power for operation, but electrical noise from the power supply corrupts the data being written
Solution Approach 1:
The power supply connection is segmented into separate operational phases: during write and write-back cycles, the power supply is disconnected from the memory array while remaining connected to peripheral circuits. This segmentation allows the memory to operate in an isolated, low-noise environment during critical write operations, while still maintaining overall system functionality through selective power distribution.
Solution Approach 2:
A power supply isolation switch acts as an intermediary component between the power supply and the memory array. This switch controls the timing of power connection and disconnection, enabling the system to selectively isolate the memory from power supply noise during write operations while maintaining power supply to other system components that require continuous operation.
2Object-affected harmful factors
If the power supply is disconnected during write cycles to reduce noise, then electrical noise interference is reduced, but the memory cannot receive power for operation
Solution Approach 1:
The power distribution system is segmented into multiple independent paths: one path supplies power to the memory array (which can be isolated during writes), while another path supplies power to peripheral circuits and control logic (which remain active). This allows selective power disconnection from only the memory array during write operations, maintaining overall system power availability while reducing noise during critical operations.
Solution Approach 2:
The power supply isolation switch is activated in advance before write operations begin, preemptively disconnecting the memory array from the power supply to prevent noise contamination. This preliminary isolation ensures that no electrical noise from the power supply can interfere with the write operation, while the switch timing is coordinated to maintain power availability to other system components throughout the write cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the write and write-back signal margin by reducing electrical noise interference, ensuring data integrity and stability during these critical operations.
Implementation Method 1
Energy during the write-back cycle or the write cycle is provided by one or more capacitors
Implementation Method 2
Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors
Data Source
AI summary
In an embodiment of the invention, a method is provided for isolating a ferroelectric memory from a power supply during a write-back cycle or a write cycle of the ferroelectric memory. After it is determined that a write-back cycle or a write cycle will occur in the ferroelectric memory, the power supply is electrically disconnected from the ferroelectric memory before a write-back cycle or a write cycle occurs. Energy during the write-back cycle or the write cycle is provided to the ferroelectric memory by one or more capacitors in this embodiment. After the write-back cycle or the write cycle has ended, the power supply is electrically connected to the ferroelectric memory and the capacitors.