Ferroelectric Memory Stack With Oxygen Scavenging Interface Control

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Solution Overview

Problem

The semiconductor industry faces challenges in reducing the quality of ferroelectric memory devices due to the formation of undesired interfacial layers between oxide semiconductor and ferroelectric layers, which affect device performance and endurance, especially as feature sizes decrease.

Innovation Solution

Incorporating an oxygen scavenging layer between the ferroelectric and conductive layers to absorb oxygen, thereby preventing the formation of defective interfacial layers and improving the channel surface quality, using materials like Hf, La, Al, TiSiN, or TiAl for effective scavenging.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If oxide semiconductor and ferroelectric layers are deposited directly adjacent to each other, then the manufacturing process is simple, but undesired interfacial layers form between them degrading device quality

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidinterface quality
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

A sacrificial layer is introduced between the oxide semiconductor layer and the ferroelectric layer. This sacrificial layer acts as an intermediary that prevents direct contact between the oxide semiconductor and ferroelectric materials, thereby avoiding the formation of undesired interfacial layers. The sacrificial layer is subsequently removed to create a clean interface without direct oxide-ferroelectric contact.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If feature sizes are reduced to increase integration density, then more components can be integrated, but device quality and performance deteriorate

Engineering Contradiction:
Improveintegration densityVSAvoiddevice quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The sacrificial layer serves as a mediator that enables precise control of the interface between oxide semiconductor and ferroelectric layers at reduced feature sizes. By preventing direct contact and interdiffusion, the sacrificial layer maintains high interface quality even when dimensions are scaled down, thus preserving device performance while enabling higher integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If an oxygen scavenging layer is added to prevent interfacial layer formation, then channel surface quality improves, but device complexity increases

Engineering Contradiction:
Improvechannel surface qualityVSAvoidlayer structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The sacrificial layer functions as an oxygen scavenging intermediary that absorbs or reacts with oxygen during the deposition process, preventing oxygen from forming interfacial layers at the oxide semiconductor-ferroelectric interface. This intermediary approach improves channel surface quality by eliminating oxygen-related defects while adding only a single sacrificial layer that can be removed later.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in an interfacial-layer-free memory device with enhanced performance and reduced errors in reading digital values, improving the overall quality and reliability of ferroelectric memory devices.

Implementation Method 1

Incorporating an oxygen scavenging layer between the ferroelectric and conductive layers to absorb oxygen, thereby preventing the formation of defective interfacial layers

Methodology Applied
Scientific EffectOxygen scavenging: Absorption (physical)

Data Source

PatentUS20240381654A1Ferroelectric memory device and method of forming the same
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240381654A1 patent drawing
  • US20240381654A1 patent drawing
  • US20240381654A1 patent drawing

AI summary

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a multi-layer stack disposed on a substrate and having a plurality of conductive layers interleaved between a plurality of dielectric layers. A channel layer is arranged along a side of the multi-layer stack. A ferroelectric material is arranged between the channel layer and the side of the multi-layer stack. A plurality of oxygen scavenging layers are respectively arranged between the ferroelectric material and sidewalls of the plurality of conductive layers. The plurality of oxygen scavenger layers are entirely confined below the plurality of dielectric layers.