Ferroelectric Memory Device with Horizontal and Vertical Parity Check Arrays
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Solution Overview
Problem
In nonvolatile ferroelectric memory devices, randomly distributed cell data and failed cell corrections pose challenges in effectively repairing and utilizing failed cells, especially when a 1-bit failure occurs in a predetermined column.
Innovation Solution
The implementation of a nonvolatile ferroelectric memory device that includes a main memory cell array, horizontal parity check cell arrays, vertical parity check cell arrays, and an error correcting code processing unit to check and correct errors by comparing code data stored in these arrays, thereby normalizing data in the main memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity check cell arrays are added to correct failed cells, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent divides the parity check function into two independent segments: horizontal parity check cell array and vertical parity check cell array. Each array handles parity checking in one dimension separately, which simplifies the correction process and reduces the complexity of the error correction circuit compared to a single comprehensive parity check system.
Solution Approach 2:
The patent introduces a second dimension of parity checking by adding vertical parity check cell arrays alongside the horizontal ones. This dimensional approach allows the system to correct errors by checking both row-wise and column-wise parity, thereby improving reliability without requiring an overly complex single-dimension system.
2Reliability
If multiple parity check arrays are implemented, then error correction capability is improved, but manufacturing complexity increases
Solution Approach 1:
The horizontal and vertical parity check cell arrays use the same basic cell structure and operating principles, allowing them to be manufactured using identical fabrication processes. This universality simplifies manufacturing compared to implementing different types of check circuits, as the same manufacturing流程 can be reused for both horizontal and vertical parity checking.
Data Source
AI summary
A nonvolatile ferroelectric memory device including a failed cell correcting circuit which effectively processes randomly distributed cell data. The nonvolatile ferroelectric memory device checks horizontal parity of a main memory cell array and stores the parity in a horizontal parity check cell array, and checks vertical parity of a main memory cell array and stores the parity in the vertical parity check cell array. Then, code data stored in the horizontal parity check cell array and the vertical parity check cell array are compared to sensing data of the main memory cell to correct an error datum. As a result, a 1 bit failure randomly generated within a predetermined column is corrected.