Ferroelectric Memory Cell Multi-State Storage
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Solution Overview
Problem
Non-volatile solid-state EEPROM memories face challenges in cost reduction, write time efficiency, and limited state storage due to the need for multiple sense amplifiers and complex 'garbage collection' procedures, which increase costs and limit their lifetime in applications requiring frequent data rewriting.
Innovation Solution
A ferroelectric memory system utilizing ferroelectric capacitors with multiple states, where the state of polarization is controlled by varying the charge stored, allowing for efficient read and write operations by measuring the charge transferred, and implementing a readout circuit to determine the stored state, thereby reducing the need for multiple sense amplifiers and simplifying data management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If multi-state memory cells are used to store multiple bits per cell, then memory cost is reduced, but write time increases significantly
Solution Approach 1:
The patent segments the write operation into two distinct phases: a fast program operation that writes data to the ferroelectric capacitor, and a separate verify operation that checks the written data. This segmentation allows the bulk of the write time to be reduced while maintaining data integrity through the subsequent verification step.
Solution Approach 2:
The patent utilizes the ferroelectric material's ability to maintain multiple stable polarization states as a fundamental parameter change. By programming the ferroelectric capacitor to different polarization states corresponding to different data values, the system achieves multi-state storage with faster write times compared to conventional charge-based multi-state cells.
2Productivity
If the number of sense amplifiers is increased to read/write multiple cells simultaneously, then productivity improves, but device complexity and cost increase
Solution Approach 1:
The patent employs a single sense amplifier that is time-multiplexed to service multiple memory cells sequentially. The verify operation allows the same sense amplifier to be reused for different cells after the initial program operation, eliminating the need for multiple dedicated sense amplifiers while maintaining the ability to read and verify data from multiple cells.
3Adaptability or versatility
If conventional EEPROM cells are used with frequent rewriting, then adaptability is maintained, but reliability decreases due to limited erase/write cycles
Solution Approach 1:
The patent exploits the ferroelectric capacitor's ability to be rapidly programmed and verified without the degradation issues of conventional floating gate cells. The fast verify operation allows for immediate detection and correction of programming errors, effectively creating a disposable-like write operation that can be performed frequently without compromising the overall reliability of the memory cell.
4Adaptability or versatility
If garbage collection procedures are implemented to manage erased records, then adaptability is improved, but device complexity and cost increase
Solution Approach 1:
The fast verify operation enabled by the ferroelectric capacitor's properties allows the memory system to self-check written data immediately after programming. This self-verification capability eliminates the need for complex background garbage collection procedures, as programming errors can be detected and corrected in real-time without requiring separate data management operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cost and increases the efficiency of data storage and retrieval, allowing for more states to be stored per cell, thus extending the memory's lifetime and reducing the time required for write operations.
Implementation Method 1
each state corresponds to a different amount of charge being transferred to the gate
Implementation Method 2
A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line
Implementation Method 3
A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value
Data Source
AI summary
A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.