Ferroelectric Memory Precharge Circuit Low Voltage Read Margin
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Solution Overview
Problem
Conventional ferroelectric memories face challenges in error-free data reading at low power supply voltages due to reduced read margin, leading to potential erroneous operations.
Innovation Solution
The implementation of a ferroelectric memory with a memory cell array, a reset circuit, a precharge circuit, and a timing control mechanism that drives the plate line and word line to increase the potential difference across bit lines, independent of parasitic capacitance, ensuring accurate data reading even at low power supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power supply voltage is reduced to lower power consumption, then energy efficiency is improved, but the read margin decreases leading to erroneous operations
Solution Approach 1:
The patent applies preliminary action by precharging the bit lines to a high potential level before the read operation. The timing control circuit generates a precharge signal that activates the precharge circuit to charge the bit lines to VDD potential before the word line is activated. This preliminary charging ensures that when the read operation occurs at low supply voltage, there is sufficient initial potential difference to maintain reliable reading despite the reduced voltage headroom.
Solution Approach 2:
The patent changes the timing parameters of the read operation by introducing a delayed activation of the word line relative to the plate line. The timing control circuit delays the word line activation by a predetermined period after the plate line activation, allowing the potential difference to build up gradually. This parameter change optimizes the read margin at low supply voltages by controlling the timing sequence of voltage application.
2Device complexity
If the conventional voltage division method is used for reading, then the circuit complexity is reduced, but the potential difference across bit lines becomes insufficient at low power supply voltages
Solution Approach 1:
The patent introduces a precharge circuit that performs preliminary charging of the bit lines to VDD potential before the read operation. This preliminary action creates a high initial potential on the bit lines, which then develops a larger potential difference when the selected memory cell is accessed. The precharge circuit includes PMOS transistors controlled by a precharge signal from the timing control circuit, adding minimal complexity while significantly improving the potential difference at low supply voltages.
Solution Approach 2:
The patent makes the bit line potential dynamic by introducing a time-varying precharge sequence. The bit lines are dynamically charged to high potential before reading, then allowed to discharge through the selected memory cell during the read operation. This dynamic approach creates a larger transient potential difference that can be reliably detected by the sense amplifier, overcoming the limitations of static voltage division at low supply voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the read margin at low power supply voltages, enabling error-free data reading by maintaining a significant potential difference across bit lines, thus preventing erroneous operations.
Implementation Method 1
The ferroelectric capacitors Cai, Cbi have hysteresis characteristics, in which a remanent polarization occurs even when the electric field is decreased to zero after applying an electric field across the electrodes.
Implementation Method 2
a potential appears on the bit line BL which is voltage-divided by the parasitic capacitance between the bit line BL and the ground potential GND, and the ferroelectric capacitor Ca0
Data Source
AI summary
A ferroelectric memory, upon reading of a memory cell array, in which the plate line PL is charged to the power supply potential VDD by a driving control circuit prior to driving of the relevant word line WL. The bit lines BL and /BL are charged to the potential VDD by a timing control circuit, then the word line WL is driven. At this time, the lines BL and /BL are discharged by applying an equalizing signal EQ with predetermined pulse width to a reset circuit.