3D Ferroelectric Memory Channel Structure for Read Disturb Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High voltage application during read operations in semiconductor memory devices can degrade reliability and cause performance issues due to the formation of channels in unselect memory cells, leading to read disturb phenomena.
Innovation Solution
The implementation of a back gate electrode and a back gate voltage applied during read operations in semiconductor memory devices, along with controlled voltages to unselect word lines, to stabilize channel formation and reduce read disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If high voltage is applied to the target cell and other cells for channel formation during read operation, then read operation can be performed, but reliability of the memory cell degrades due to read disturb phenomena
Solution Approach 1:
The gate structure is segmented into multiple independent gate electrodes (first gate electrode, second gate electrode, third gate electrode) that can be controlled separately. This allows selective application of voltages to different regions, enabling read operations on target cells while preventing channel formation in unselect memory cells through controlled depletion regions.
Solution Approach 2:
Different voltage conditions are applied to different spatial regions of the memory device. The target cell region receives appropriate voltages for channel formation and read operation, while unselect memory cell regions are maintained in depletion state through specific gate electrode voltage control, creating locally optimized conditions for each region.
2Quantity of substance
If three-dimensional arrangement of memory cells is implemented to increase data storage capacity, then storage capacity increases, but complexity of the device structure increases
Solution Approach 1:
The memory device transitions from two-dimensional to three-dimensional arrangement by stacking multiple gate electrodes and memory cells vertically. The channel structure extends in the vertical direction through the stacked gate electrodes, enabling increased storage capacity by utilizing the third dimension while maintaining a compact footprint.
Solution Approach 2:
Multiple gate electrodes and memory cells are nested within each other in a vertical stack configuration. The channel structure passes through multiple layers of gate electrodes, creating a nested arrangement where smaller structures are contained within larger ones, maximizing space utilization for data storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor memory devices by stabilizing channel formation and reducing read disturb, thereby improving data retention and read accuracy.
Implementation Method 1
a channel structure extending through the mold structure and including a ferroelectric layer, a channel layer, and a back gate electrode stacked in turn on a side surface of the plurality of gate electrodes
Implementation Method 2
during a read operation of a select memory cell of the plurality of memory cells, a back gate voltage may be applied to the back gate electrode of the channel structure
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An example semiconductor memory device includes a cell substrate (100), a mold structure (MS), and a channel structure (CH1). The cell substrate includes a first side (100a) and a second side (100b) opposite to the first side. The mold structure includes a plurality of gate electrodes (124) and a plurality of mold insulating films (110) alternately stacked on the first side of the cell substrate. The channel structure extends through the mold structure and includes a ferroelectric layer (132), a channel layer (134), and a back gate electrode (138) stacked in turn on a side surface of the plurality of gate electrodes. The plurality of gate electrodes and the channel structure may define a plurality of memory cells, and during a read operation of a select memory cell of the plurality of memory cells, a back gate voltage may be applied to the back gate electrode of the channel structure.