3D Ferroelectric Memory Array Layout for Read-Stable Data Retention
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Solution Overview
Problem
Existing memory technologies face challenges in maintaining non-volatile data storage due to the reversible nature of ferroelectric capacitors during read operations, which often require immediate rewriting of memory cells after data retrieval.
Innovation Solution
The implementation of memory arrays with vertically-alternating tiers of insulative material and memory cells comprising both transistors and capacitors, where the capacitors utilize ferroelectric materials for non-volatile storage, and the transistors are designed with horizontally-oriented channel regions for efficient current flow, along with access-line pillars and sense lines for controlled data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If ferroelectric capacitors are used for non-volatile storage, then data retention is improved, but the reversible nature of ferroelectric materials during read operations causes memory states to change, requiring immediate rewriting
Solution Approach 1:
The memory cell is divided into two independent components: a ferroelectric capacitor for non-volatile data storage and a transistor for controlled data access. This segmentation allows the capacitor to maintain data without being affected by read operations, while the transistor controls when data is read, preventing unwanted state changes during read operations.
Solution Approach 2:
The transistor acts as an intermediary between the read operation and the ferroelectric capacitor. It controls the flow of read operations, allowing data to be read only when the transistor is activated, thereby protecting the capacitor's stored state from unintended changes during read operations.
2Manufacturing precision
If vertically-alternating tiers of insulative material and transistor material are formed, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The memory array is organized in vertically-alternating tiers, stacking insulative material and transistor material layers in the vertical dimension. This vertical stacking allows precise alignment of memory cell components through layer-by-layer fabrication, improving manufacturing precision while managing complexity through systematic layering.
Solution Approach 2:
The vertically-alternating tiers create a nested structure where insulative material layers are interleaved with transistor material layers. Each layer is formed within the context of the previous layers, creating a precisely aligned multi-layer structure that improves manufacturing precision through controlled sequential deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the stability of memory states, allowing for reliable non-volatile data storage without immediate rewriting after read operations, improving the retention of memory states and reducing the need for frequent rewrites.
Implementation Method 1
One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell.
Implementation Method 2
A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material.
Implementation Method 3
A field effect transistor is one type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region.
Data Source
AI summary
A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed.