Ferroelectric Memory Refresh Control via Plate Line Potential Equality
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional ferroelectric memories face reliability issues due to charge leakage and instability when word lines are not associated with plate lines in a one-to-one correspondence, making it difficult to perform refresh operations, especially during frequent read and write accesses.
Innovation Solution
A ferroelectric memory design that includes a memory cell array with multiple word lines, bit lines, and plate lines, where the refresh operation is performed when the plate line and bit line connected to the selected cell are at the same potential, allowing for background refresh operations without interrupting access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a refresh operation is performed periodically to release stored charges, then reliability is improved, but the refresh operation cannot be performed when accesses for reading and/or writing are performed frequently
Solution Approach 1:
The patent applies dynamics by making the refresh operation timing flexible and adaptive rather than fixed. The refresh control circuit dynamically determines when to perform refresh operations based on the current operational state of the memory, specifically monitoring whether plate lines and bit lines are at the same potential. This allows the system to adapt refresh operations to frequent access patterns while maintaining reliability.
Solution Approach 2:
The refresh control circuit performs self-service by autonomously monitoring the potential states of plate lines and bit lines, and independently deciding when to execute refresh operations without external intervention. This self-monitoring and self-adjusting mechanism enables the system to maintain reliability even during frequent access operations.
2Productivity
If the plate line and bit line are maintained at different potentials to support frequent access operations, then productivity is improved, but the refresh operation cannot be performed
Solution Approach 1:
The patent applies periodic action by performing refresh operations at appropriate intervals rather than continuously or at fixed periodic times. The refresh control circuit monitors the potential states and executes refresh operations periodically when the conditions are favorable (when plate line and bit line are at the same potential), balancing productivity and reliability.
Solution Approach 2:
The patent ensures continuity of useful action by seamlessly integrating refresh operations into the normal access operation flow. Rather than interrupting access operations for refresh, the system continuously performs both access and refresh operations by selecting appropriate timing when line potentials are equal, maintaining both productivity and reliability.
3Quantity of substance
If word lines are not associated with plate lines in one-to-one correspondence to increase memory capacity, then quantity of substance is improved, but charge leakage and instability occur
Solution Approach 1:
The patent applies universality by making plate lines serve multiple functions: they are used both for normal access operations (along with word lines) and for refresh operations. The same plate lines that enable increased memory capacity through non-one-to-one association with word lines are also utilized for refreshing charges, eliminating the need for separate refresh infrastructure and maintaining reliability in high-capacity configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient refresh operations to be performed during idle times between access operations, increasing the frequency of refreshes as access operations increase, thereby maintaining memory reliability even during frequent data access.
Implementation Method 1
A ferroelectric memory is a semiconductor memory including a ferroelectric capacitor as a component of a memory cell
Implementation Method 2
a refresh operation of turning on a word line to release the charges
Data Source
AI summary
A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation.