Ferroelectric Memory Refresh Cycle Optimization
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Solution Overview
Problem
Conventional DRAMs perform refresh operations by continuously conducting read and write operations in synchronization with an internal clock having a shorter cycle than the external clock, leading to increased internal and external access times, which hinders efficient data storage and retrieval in ferroelectric memories.
Innovation Solution
A memory system with an access control portion for internal access, a refresh control portion that divides the refresh operation into read and rewrite operations, and an address determination portion to synchronize refresh operations with external access, allowing for efficient data management and reduced access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh operation is performed by continuously conducting read and write operations in synchronization with an internal clock having a shorter cycle than the external clock, then the refresh operation can be performed without hindering internal access operation, but the cycle of the internal clock is increased and the external access operation period becomes longer
Solution Approach 1:
The refresh operation is segmented into a read operation phase and a rewrite operation phase that are executed separately and alternately. This segmentation allows the system to perform refresh operations without continuously occupying the internal clock, thereby reducing the impact on external access operation timing while still achieving effective data refresh.
Solution Approach 2:
The patent implements periodic refresh operations where the read and rewrite operations are performed in alternating periods rather than continuously. The internal clock generates cycles that include both refresh phases and idle phases, allowing external access operations to proceed during idle periods. This periodic structure reduces the overall cycle time impact on external access operations.
2Reliability
If the internal clock cycle is shortened to perform refresh operations more frequently, then data deterioration is reduced, but the external access operation period increases
Solution Approach 1:
The system dynamically adjusts the timing and frequency of refresh operations based on the state of external access operations. The internal clock is configured to generate refresh cycles that adapt to external access patterns, performing refresh operations during periods when external access is not required. This dynamic timing optimization ensures data retention quality while minimizing impact on external access speed.
Data Source
AI summary
A memory includes an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation, a refresh division control portion dividing the refresh operation into a read operation and a rewrite operation and an address determination portion determining whether or not an address to be subjected to the refresh operation and an address to be subjected to the external access operation during the refresh operation coincide with each other.