Ferroelectric Crossbar Memory With RC-Tuned Selector Disturbance Control
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Solution Overview
Problem
Traditional ferroelectric materials face integration challenges with CMOS processes, leading to high bit-flipping issues and disturbances in crossbar array memories due to wide coercive field distribution and RC delay variations, which are not effectively addressed by existing resistive switching selectors.
Innovation Solution
A crossbar array ferroelectric capacitor memory with a stacked structure of a top electrode, resistive switching dielectric layer, intermediate metal layer, ferroelectric dielectric layer, and bottom electrode, where the resistive switching selector transitions to a low resistance state under full-swing voltage, reducing RC delay for selected cells and maintaining high resistance for disturbed cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ferroelectric materials (PZT, BTO) are used, then ferroelectric memory can achieve low power consumption and high speed, but they have low compatibility with CMOS processes and show obvious size effects, making integration at advanced process nodes impossible
Solution Approach 1:
The patent changes the material parameter from traditional perovskite ferroelectric materials (PZT, BTO) to hafnium oxide (HfO2)-based ferroelectric materials. This parameter change enables CMOS compatibility while maintaining ferroelectric memory functionality, resolving the contradiction between performance and manufacturability.
Solution Approach 2:
The patent uses composite material structures including HfO2-based ferroelectric layers combined with resistive switching dielectric layers and intermediate metal layers. This composite approach achieves both CMOS compatibility and effective ferroelectric memory performance.
2Ease of manufacture
If HfO2-based ferroelectric materials are used, then CMOS compatibility and integration are improved, but the coercive field distribution becomes wide, causing significant disturbances to unselected cells and serious bit-flipping problems
Solution Approach 1:
The patent segments the memory cell structure into distinct functional layers: resistive switching dielectric layer, intermediate metal layer, and ferroelectric dielectric layer. This segmentation allows independent optimization of each layer's properties to reduce cell disturbance while maintaining CMOS compatibility.
Solution Approach 2:
The patent introduces an intermediate metal layer as a mediator between the resistive switching dielectric layer and the ferroelectric dielectric layer. This intermediary layer helps control the electric field distribution and reduces the harmful effects of wide coercive field distribution, minimizing bit-flipping in unselected cells.
3Object-affected harmful factors
If resistive switching selector is added in series to increase RC delay, then disturbance to unselected cells is reduced, but the approach ignores capacitance value differences at different voltages, so RC delay is not high enough at lower voltages
Solution Approach 1:
The patent changes the voltage parameter by applying different voltage conditions to selected and unselected cells. Selected cells receive full-swing voltage to activate the resistive switching selector and reduce RC delay, while unselected cells receive only half-select voltage, maintaining high RC delay and reducing disturbance. This parameter-based differentiation achieves both goals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure significantly reduces read/write disturbances and bit error rates while maintaining a larger storage window by stabilizing ferroelectric capacitance and minimizing voltage drop in disturbed cells.
Implementation Method 1
the resistive switching selector transitions to a low resistance state under full-swing voltage, reducing RC delay for selected cells and maintaining high resistance for disturbed cells
Implementation Method 2
the ferroelectric dielectric layer has a spontaneous polarization intensity that can be reversed by an external voltage, enabling non-volatile storage of data
Implementation Method 3
when the voltage is high enough, the oxygen vacancies in the resistive switching selector or the metal atoms of the electrodes undergo directional migration and form conductive metal filaments that penetrate through the resistive switching dielectric layer
Data Source
AI summary
A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.