Ferroelectric-Paraelectric Memory Stack for Higher 3D Data Retention
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Solution Overview
Problem
There is a demand for semiconductor devices capable of storing a large amount of data, and existing methods to increase data storage capacity, such as three-dimensionally arranged memory cells, have not been fully optimized.
Innovation Solution
A semiconductor device is designed with a stacked structure comprising gate electrodes and interlayer insulating layers, featuring ferroelectric and paraelectric layers with different crystal structures, and electron trap layers, which enhance data storage capacity by optimizing the arrangement and properties of these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally arranged memory cells are used instead of two-dimensionally arranged memory cells, then data storage capacity is increased, but device complexity increases
Solution Approach 1:
The crystalline layer is segmented into multiple functional sub-layers: ferroelectric layers (for data storage), paraelectric layers (for isolation and electrical property control), and electron trap layers (for charge management). This segmentation allows each sub-layer to perform its specific function optimally, enabling high-density 3D storage while maintaining manageable device complexity through modular design
Solution Approach 2:
The patent transitions from 2D memory cell arrangement to 3D stacked structure with alternating ferroelectric and paraelectric layers extending vertically. This dimensional change enables significantly increased storage capacity by utilizing the vertical dimension, with multiple memory layers stacked above each other sharing common bit lines and word lines
2Reliability
If ferroelectric layers and paraelectric layers with different crystal structures are stacked, then data retention is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes phase transitions and crystal structure changes of the same material (HfO2) under different processing conditions to create distinct ferroelectric and paraelectric layers. By controlling deposition parameters, annealing temperature, and oxygen partial pressure, the material transforms between phases, enabling precise control of electrical properties without requiring different materials, thus maintaining manufacturing feasibility
Solution Approach 2:
The patent creates a composite structure using the same base material (HfO2) in different crystalline phases arranged in alternating layers. This composite approach combines the ferroelectric phase (for data storage) and paraelectric phase (for electrical isolation and threshold control) to achieve enhanced data retention while simplifying the manufacturing process by using a single material system
3Productivity
If electron trap layers are positioned between crystalline layer and gate electrodes, then data storage efficiency is improved, but device complexity increases
Solution Approach 1:
The electron trap layers serve multiple functions simultaneously: they trap electrons to enable charge storage, control threshold voltages of transistor channels, and work in conjunction with the ferroelectric and paraelectric layers to achieve efficient data storage. This multi-functionality improves data storage efficiency without proportionally increasing device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design increases data storage capacity and efficiency by leveraging the unique properties of ferroelectric and paraelectric layers, allowing for improved data retention and access speeds.
Implementation Method 1
the crystalline layer comprises a plurality of ferroelectric layers each at a height corresponding to one of the plurality of gate electrodes, and a plurality of paraelectric layers each at a height corresponding to one of the plurality of interlayer insulating layers, and the plurality of ferroelectric layers and the plurality of paraelectric layers have different crystal structures while containing the same material
Implementation Method 2
the plurality of ferroelectric layers and the plurality of paraelectric layers have different crystal structures while containing the same material
Implementation Method 3
an electron trap layer outside the crystalline layer such that the crystalline layer is between the electron trap layer and the channel poly layer
Data Source
AI summary
Provided is a semiconductor device including a substrate, a stacked structure including a plurality of gate electrodes and a plurality of interlayer insulating layers, and a plurality of channel structures penetrating the stacked structure. Each of the plurality of channel structures includes a channel poly layer, a crystalline layer including hafnium (Hf) or zirconium (Zr), an electron trap layer, and a plurality of gate insulating layers positioned between the electron trap layer and the plurality of gate electrodes at a height corresponding to the plurality of gate electrodes. The crystalline layer includes a plurality of ferroelectric layers positioned at a height corresponding to the plurality of gate electrodes, and a plurality of paraelectric layers positioned at a height corresponding to the plurality of interlayer insulating layers. The plurality of ferroelectric layers and the plurality of paraelectric layers have different crystal structures while containing the same material.