Ferroelectric 3D Memory Stack for Density and Structural Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory technologies face challenges in achieving high memory cell density and structural stability due to limitations in the aspect ratio of the multilayer stack, which affects the performance and reliability of memory arrays.
Innovation Solution
The implementation of a memory array structure with a staircase arrangement of word lines and the use of anti-oxidation metal layers to prevent dielectric interface formation, combined with a manufacturing process that includes multiple patterning and etching techniques to form conductive features and ferroelectric strips, enhances memory cell density and structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the aspect ratio of the multilayer stack is increased to improve memory cell density, then the memory cell density improves, but the structural stability deteriorates
Solution Approach 1:
The patent divides the continuous multilayer stack into discrete segments by introducing sacrificial layers between stacked conductive layers. These sacrificial layers create physically separated segments that can be independently supported, preventing structural collapse while maintaining high vertical density. The segmentation allows each layer to be stabilized individually rather than relying on the entire stack's integrity.
Solution Approach 2:
The patent introduces sacrificial layers as intermediary elements between the conductive layers of the multilayer stack. These intermediary sacrificial layers provide mechanical support and prevent direct contact between adjacent conductive layers, thereby maintaining structural stability during the high aspect ratio configuration. The intermediaries act as spacers that preserve the integrity of each layer while enabling close stacking.
2Manufacturing precision
If multiple patterning and etching techniques are used to form conductive features, then the manufacturing precision improves, but the device complexity increases
Solution Approach 1:
The patent applies preliminary patterning actions to define the footprints of conductive features before forming the multilayer stack. By pre-defining the lateral boundaries and positions of conductive features through initial patterning steps, subsequent etching and deposition processes can proceed with higher precision without requiring complex real-time alignment. The preliminary patterns serve as templates that guide the formation of precise conductive structures.
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical stacking to achieve higher precision. By forming conductive features in multiple vertical layers with controlled lateral offsets, the patent achieves precise feature definition through the addition of the vertical dimension. This dimensional transition allows complex three-dimensional conductive patterns to be formed through sequential layering rather than complex single-plane lithography.
Data Source
AI summary
A memory device includes a stack, a first conductive pillar and a second conductive pillar, a channel material and a ferroelectric (FE) material. The stack includes alternating a plurality of conductive layers and a plurality of dielectric layers. The plurality of conductive layers each includes a bulk layer, and the bulk layer includes a first metal layer and a second metal layer connected to the first metal layer. The first conductive pillar and the second conductive pillar are through the stack and isolating each other. The channel material is disposed in the stack. The FE material is disposed between the channel material and the second metal layer. The FE material and the channel material are disposed between the second metal layer and the first conductive pillar, and between the second metal layer and the second conductive pillar.