Ferroelectric Memory Stack with Variable Semiconductor Thickness
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Solution Overview
Problem
Current ferroelectric-based memory devices face limitations in achieving high areal data density as the size of individual transistors decreases, necessitating innovative approaches to enhance data storage capacity.
Innovation Solution
The development of a ferroelectric stack structure for memory devices, comprising a ferroelectric switching layer sandwiched between a bottom and top electrode, with a dielectric and semiconductor layer configuration that allows for multiple depletion regions and tunnel lengths, enabling multi-level cell functionality and increased data storage density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional single-level cell ferroelectric memory structure is used, then device structure is simple, but areal data density is limited
Solution Approach 1:
The patent transitions from single-level cell to multi-level cell architecture, utilizing vertical stacking of multiple ferroelectric layers between electrodes. This dimensional change from planar to three-dimensional stacking enables multiple storage levels within the same footprint, significantly increasing areal data density without proportionally increasing device complexity
Solution Approach 2:
The memory structure is segmented into multiple ferroelectric layers (first ferroelectric layer, second ferroelectric layer, third ferroelectric layer) with intermediate electrodes, allowing each layer to store independent data. This segmentation enables multi-level cell functionality where combinations of layer states create multiple resistance levels for enhanced storage capacity
2Quantity of substance
If transistor size is reduced to increase areal density, then more devices fit per chip area, but manufacturing precision requirements increase
Solution Approach 1:
Instead of continuing to scale transistor dimensions laterally, the patent utilizes vertical stacking of ferroelectric layers to increase device capacity. This approach shifts the density improvement from lateral scaling to vertical dimensionality, avoiding the escalating manufacturing precision requirements associated with sub-10nm transistor fabrication
Solution Approach 2:
The patent changes the storage mechanism from single-bit per cell to multi-bit per cell by utilizing multiple resistance levels achievable through different polarization states across stacked ferroelectric layers. This parameter change in storage capacity per device allows higher areal density without requiring smaller transistor geometries
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables higher areal data density by allowing multiple resistance levels and polarization states, effectively increasing the storage capacity of ferroelectric memory devices beyond traditional single-level cell capabilities.
Implementation Method 1
depositing a ferroelectric layer over the semiconductor layer
Implementation Method 2
depositing a semiconductor layer over the bottom electrode layer, the semiconductor layer including a plurality of portions with different thicknesses
Data Source
AI summary
A method according to the present disclosure includes forming a bottom electrode layer over a substrate, forming an insulator layer over the bottom electrode layer, depositing a semiconductor layer over the bottom electrode layer, depositing a ferroelectric layer over the semiconductor layer, forming a top electrode layer over the ferroelectric layer, and patterning the bottom electrode layer, the insulator layer, the semiconductor layer, the ferroelectric layer, and the top electrode layer to form a memory stack. The semiconductor layer includes a plurality of portions with different thicknesses.