Ferroelectric Memory Array Switching for Data Integrity
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Solution Overview
Problem
Ferroelectric memory cells are susceptible to data loss due to electrical fluctuations in the memory array, causing minor influences to accumulate and disrupt the stored data state.
Innovation Solution
Implementing a switch between the ferroelectric capacitor and the voltage source to short out the capacitor during operation, except for access intervals, which provides electrical isolation and protects the memory cell from disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the ferroelectric capacitor is electrically coupled to the voltage source during operation, then the capacitor can be accessed for read/write operations, but electrical fluctuations in the memory array cause data loss due to accumulated minor influences
Solution Approach 1:
The patent segments the electrical connection to the ferroelectric capacitor by introducing a switch that isolates the capacitor from the voltage source during non-access periods. This segmentation allows the capacitor to be accessed when needed while protecting it from electrical fluctuations during idle periods, thereby resolving the contradiction between operational accessibility and data integrity.
Solution Approach 2:
The patent implements preliminary action by pre-configuring the switch to be in the closed state during non-access intervals, establishing electrical isolation before electrical fluctuations can accumulate and cause data loss. This proactive isolation prevents the harmful effects of electrical noise before they can impact the stored data, while still allowing rapid access when required.
2Reliability
If the ferroelectric capacitor is isolated from the voltage source to protect from electrical fluctuations, then data integrity is maintained, but the capacitor cannot be accessed for read/write operations
Solution Approach 1:
The patent applies dynamics by making the electrical connection state changeable through a controllable switch that transitions between open and closed states based on access requirements. This dynamic configuration allows the system to adapt between isolation mode (for data integrity) and access mode (for read/write operations), resolving the contradiction between reliability and operational ease.
Solution Approach 2:
The switch serves as an intermediary element between the ferroelectric capacitor and the voltage source, mediating the electrical connection based on operational needs. This intermediary allows the system to achieve both data integrity (through isolation) and access capability (through controlled connection) by intelligently managing the electrical coupling state.
3Reliability
If a switch is added to control electrical isolation of the ferroelectric capacitor, then data integrity is protected from electrical fluctuations, but device complexity increases
Solution Approach 1:
The patent implements self-service by integrating the switch control logic into the existing memory array control architecture, allowing the isolation mechanism to be automatically managed by the memory controller without requiring external control circuits. This approach protects data integrity while minimizing the increase in device complexity by utilizing existing control resources.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively preserves the integrity of the data state by shielding the ferroelectric capacitor from electrical fluctuations, preventing data loss and maintaining the memory cell's stability.
Implementation Method 1
a parallel orientation of a magnetic spin within the ferroelectric capacitor may correspond to a first data state, and an antiparallel orientation of the magnetic spin may correspond to a second data state
Implementation Method 2
Implementing a switch between the ferroelectric capacitor and the voltage source to short out the capacitor during operation, except for access intervals, which provides electrical isolation and protects the memory cell from disturbances
Data Source
AI summary
Some embodiments include a memory array which has rows of fins. Each fin has a first pedestal, a second pedestal and a trough between the first and second pedestals. A first source/drain region is within the first pedestal, a second source/drain region is within the second pedestal, and a channel region is along the trough between the first and second pedestals. Digit lines are electrically coupled with the first source/drain regions. Ferroelectric capacitors are electrically coupled with the second source/drain regions. Wordlines are along the rows of fins and overlap the channel regions. Conductive isolation lines are under the wordlines along the rows of fins.