3D Ferroelectric Memory Programming for Threshold Voltage Control

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in increasing data storage capacity and ensuring improved performance and reliability, particularly in three-dimensionally arranged memory cells with ferroelectric-based data storage elements.

Innovation Solution

A programming method for semiconductor memory devices involving word lines stacked vertically, a channel pattern intersecting these lines, and ferroelectric data storage between them, with initializing operations using positive or negative voltages, followed by program operations using opposite polarities to achieve enhanced threshold voltage differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases

Engineering Contradiction:
Improvedata storage capacityVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple word lines vertically and introducing a channel pattern that extends in the vertical direction. This dimensional change enables increased storage capacity within the same footprint area while maintaining feasible manufacturing processes through sequential formation steps.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If ferroelectric-based data storage elements are used, then data retention and reliability are improved, but manufacturing precision requirements increase

Engineering Contradiction:
ImprovereliabilityVSAvoidmanufacturing precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent employs a composite structure consisting of a channel pattern material, ferroelectric material, and insulating material stacked in specific layers. This composite approach leverages the advantageous properties of each material while managing their interfacial relationships through controlled formation processes, achieving reliable ferroelectric storage with manageable manufacturing precision requirements.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent performs preliminary actions by first forming the channel pattern and then sequentially depositing the ferroelectric and insulating materials. This preliminary structuring establishes a stable foundation that guides subsequent processing steps, ensuring precise positioning and thickness control of the ferroelectric layer without requiring extremely high manufacturing precision at every step.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If initializing operation applies positive voltage to word lines, then threshold voltage control is improved, but energy consumption increases

Engineering Contradiction:
Improvethreshold voltage controlVSAvoidenergy consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent utilizes parameter changes by applying different voltage polarities (positive or negative) to the channel pattern during initializing operations, and different voltage levels during program operations. This dynamic voltage control achieves precise threshold voltage adjustment in the ferroelectric layer while optimizing energy consumption by selecting appropriate voltage magnitudes and polarities for each operational phase.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the performance and reliability of semiconductor memory devices by optimizing operating voltages and speeds, facilitating multi-level data storage with improved integration and reduced cell string cross-sectional area.

Implementation Method 1

a data storage pattern including ferroelectrics between the plurality of word lines and the channel pattern

Methodology Applied
Scientific EffectFerroelectricity:

Implementation Method 2

performing an initializing operation on a plurality of memory cells corresponding to the plurality of word lines, by applying a positive (+) voltage to the plurality of word lines or by applying a negative (−) voltage to the channel pattern

Methodology Applied
Scientific EffectElectric field-induced polarization switching:

Implementation Method 3

performing a program operation on a target memory cell corresponding to a selected word line, by applying a negative (−) program voltage to the selected word line among the plurality of word lines

Methodology Applied
Scientific EffectElectric field-induced polarization switching:

Data Source

PatentUS20250285680A1Semiconductor memory device, operating method of the same, and electronic system including the same
Publication Date: 2025.09.11 SAMSUNG ELECTRONICS CO LTD
  • US20250285680A1 patent drawing
  • US20250285680A1 patent drawing
  • US20250285680A1 patent drawing

AI summary

There are provided a semiconductor memory device including a ferroelectric-based data storage element, a programming method thereof, and an electronic system. The programming method of a semiconductor memory device which includes a plurality of word lines stacked to be spaced apart from each other in a vertical direction, a channel pattern that extends in the vertical direction and intersects the plurality of word lines, and a data storage pattern including ferroelectrics between the plurality of word lines and the channel pattern, the programming method comprising, performing an initializing operation on a plurality of memory cells corresponding to the plurality of word lines, by applying a positive (+) voltage to the plurality of word lines or by applying a negative (−) voltage to the channel pattern, and performing a program operation on a target memory cell corresponding to a selected word line, by applying a negative (−) program voltage to the selected word line among the plurality of word lines, after performing the initializing operation.