Ferroelectric Memory Transistor Manufacturing via Segmented Nitridation

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Solution Overview

Problem

Conventional methods for manufacturing microelectronic circuits using hafnium dioxide ferroelectric transistors face challenges due to the adverse effects of nitridation on ferroelectric hafnium dioxide and inhomogeneous surface polarization, which affect the reliability and switching speed of logic transistors, and require separate processing steps for ferroelectric and non-ferroelectric components.

Innovation Solution

A method where insulating and metal layers for both transistors and memory transistors are produced in common steps, with the memory transistor featuring a ferroelectric capacitor connected to the gate contact, allowing for cost-efficient and protected manufacturing of microelectronic circuits with improved polarization distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If nitridation is performed to prepare silicon surface for standard transistors, then logic transistor reliability and switching speed are improved, but ferroelectric hafnium dioxide is adversely affected

Engineering Contradiction:
Improvelogic transistor reliabilityVSAvoidadverse effect on ferroelectric hafnium dioxide
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The substrate is divided into different regions (first region for standard transistors, second region for memory transistors) that undergo different processing sequences. The first region receives nitridation treatment while the second region is protected from it, allowing each region to be optimized for its specific device type without mutual interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different surface preparation methods are applied to different regions: nitridation is applied locally to the first region for standard transistors, while the second region receives alternative preparation (such as oxidation or cleaning) that preserves ferroelectric properties. This local differentiation resolves the contradiction by tailoring treatment to specific device requirements.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If ferroelectric hafnium dioxide is applied onto entire substrate before nitridation, then ferroelectric memory transistor can be formed, but subsequent nitridation degrades the ferroelectric layer

Engineering Contradiction:
Improveferroelectric memory transistor formationVSAvoidferroelectric layer performance
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

Protective structures (such as masks or protective layers) are applied to the second region before the nitridation process begins. This preliminary protection prevents the harmful nitridation from reaching the ferroelectric hafnium dioxide in the second region, allowing the ferroelectric layer to be formed and maintained without degradation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A protective intermediary layer or mask is introduced between the nitridation process and the ferroelectric hafnium dioxide. This intermediary selectively blocks the nitridation treatment from reaching the second region while allowing it to proceed in the first region, thus protecting the ferroelectric properties while enabling standard transistor fabrication.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If separate processing steps are used for ferroelectric and non-ferroelectric components, then each component type can be optimized, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvecomponent optimizationVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Multiple processing steps are merged into unified sequences where possible. For example, a single nitridation step treats both regions simultaneously, but selective masking or sequential processing ensures that only the first region receives the full nitridation treatment. This combining approach reduces the total number of separate processing steps while maintaining component-specific optimization.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The processing methodology is designed to be universal across different device types. The same basic process sequence (deposition, patterning, etching, etc.) is used for both standard and memory transistors, with regional variations achieved through masking or selective parameter adjustment rather than entirely separate process flows. This multi-functionality reduces manufacturing complexity while maintaining optimization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the manufacturing process, reduces costs, and ensures stable and efficient operation of microelectronic circuits by protecting sensitive materials and achieving homogeneous polarization distribution in ferroelectric field effect transistors.

Implementation Method 1

The discovery of ferroelectricity in materials containing hafnium dioxide (in this case with the designation FE-HfO2) has extended the application to the field of ferroelectric memories

Methodology Applied
Scientific EffectFerroelectricity:

Implementation Method 2

Ferroelectricity refers to the phenomenon that certain materials with an electrical dipole moment may change the direction of spontaneous polarization by applying an external electric field

Methodology Applied
Scientific EffectFerroelectric switching:

Data Source

PatentUS10825820B2Method for manufacturing a microelectronic circuit and corresponding microelectronic circuit
Publication Date: 2020.11.03 FRAUNHOFER GESELLSCHAFT ZUR FORDERUNG DER ANGEWANDTEN FORSCHUNG EV
  • US10825820B2 patent drawing
  • US10825820B2 patent drawing
  • US10825820B2 patent drawing

AI summary

The invention relates to a method for manufacturing a microelectronic circuit. A substrate is provided. A source contact, a bulk contact and a drain contact are each produced for a transistor and for a memory transistor. In a respective common step, an insulating layer of the transistor and an insulating layer of the memory transistor as well as a metal layer of the transistor and a metal layer of the memory transistor are produced. At least one capacitor is produced as part of the memory transistor. Gate contacts connected to the metal layer of the transistor and connected to a metal layer of the capacitor of the memory transistor, respectively, are produced. Furthermore, the invention relates to a microelectronic circuit.