Multi-Level Ferroelectric Memory via Vertical Layer Segmentation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current non-volatile memory devices, such as ferroelectric RAM (FeRAM), face challenges in achieving high integration and storage capacity while maintaining efficient operational capabilities, particularly in controlling spontaneous polarization of ferroelectric materials for effective memory operations.

Innovation Solution

A ferroelectric memory device is designed with a semiconductor substrate featuring a recess with multiple ferroelectric layers, where the source and drain are formed on either side of the recess, and a gate is positioned over the ferroelectric layers, allowing for different electric field levels to polarize the layers, enabling multi-level memory operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple ferroelectric layers are stacked to increase storage capacity, then the integration degree and storage capacity are improved, but the device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvestorage capacityVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The ferroelectric memory device is divided into multiple discrete ferroelectric layers (first ferroelectric layer, second ferroelectric layer, etc.) stacked vertically within a single memory cell. Each layer can be independently controlled by applying voltages to different gates, enabling multi-level storage without requiring multiple separate memory cells. This segmentation approach increases storage capacity while maintaining manageable device complexity through modular layering.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar storage to vertical stacking by arranging multiple ferroelectric layers in the vertical dimension. Instead of expanding storage capacity horizontally by adding more memory cells, the invention stacks layers above each other within the same footprint area, effectively utilizing the third dimension to increase storage density without proportionally increasing device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If multiple ferroelectric layers are used with different polarization levels, then the storage capacity is enhanced, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvestorage capacityVSAvoidmanufacturing precision
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

Different ferroelectric layers are designed with distinct polarization characteristics and switching voltage thresholds. The first ferroelectric layer may have different material composition or thickness compared to the second layer, enabling each layer to be selectively polarized at different electric field levels. This local differentiation allows multi-level storage while simplifying manufacturing by enabling independent control of each layer's polarization state.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent varies key parameters such as ferroelectric material composition, layer thickness, or crystal structure across different layers to create distinct polarization characteristics. By changing these parameters, each layer responds to different voltage thresholds, enabling multi-level storage without requiring extremely precise manufacturing tolerances, as the parameter variations provide inherent differentiation between layers.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If a recess structure is used to accommodate multiple ferroelectric layers, then the integration degree is improved, but the ease of manufacture decreases

Engineering Contradiction:
Improveintegration degreeVSAvoidease of manufacture
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

Multiple ferroelectric layers are nested vertically within a single recess structure formed in the semiconductor substrate. The recess acts as a container that holds the stacked layers, allowing high integration within a compact volume. This nesting approach achieves high integration degree while simplifying manufacturing compared to creating separate structures for each layer, as all layers share a common recess and substrate region.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables the ferroelectric memory device to achieve various resistance levels by selectively or simultaneously polarizing the ferroelectric layers, enhancing storage capacity and operational efficiency through the use of multiple ferroelectric layers with distinct polarization characteristics.

Implementation Method 1

The ferroelectric material may have a spontaneous polarization characteristic. A spontaneous polarization direction of the ferroelectric material may be controlled by an electric field.

Methodology Applied
Scientific EffectSpontaneous polarization: Polarisation

Implementation Method 2

The FeRAM may use a ferroelectric material as a storage medium. When a voltage or an electric field may be applied to the ferroelectric material, the ferroelectric material may be polarized in accordance with the spontaneous polarization characteristic

Methodology Applied
Scientific EffectFerroelectric effect:

Data Source

PatentUS10748930B2Multi-level ferroelectric memory device and method of manufacturing the same
Publication Date: 2020.08.18 SK HYNIX INC
  • US10748930B2 patent drawing
  • US10748930B2 patent drawing
  • US10748930B2 patent drawing

AI summary

A ferroelectric memory device may include a semiconductor substrate, a plurality of ferroelectric layers, a source, a drain and a gate. The semiconductor substrate may have a recess. The ferroelectric layers may be formed in the recess. The source may be arranged at a first side of the recess. The drain may be arranged at a second side of the recess opposite to the first side. The gate may be arranged on the ferroelectric layers. The ferroelectric layers may be polarized by different electric fields.