Ferroelectric Memory Cell Voltage Divider for Lower Write Voltage
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Solution Overview
Problem
Ferroelectric memories face issues with increased operating voltages and reduced durability due to voltage drops across interface insulation layers, leading to charge traps and leakage paths, which degrade the reliability and storage performance.
Innovation Solution
Incorporating a voltage divider capacitor, such as a high-dielectric-constant or ferroelectric capacitor, connected in parallel with the transistor to reduce the operating voltage on the ferroelectric capacitor, thereby avoiding voltage drops and reducing interface defects, enhancing durability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the write voltage or read voltage is increased to compensate for the voltage drop across the interface insulation layer, then the voltage drop is compensated, but the interface insulation layer may be electrically damaged due to the increased voltage
Solution Approach 1:
The patent introduces a charge compensation layer as an intermediary between the substrate and the ferroelectric layer. This charge compensation layer generates an electric field that compensates for the voltage drop across the interface insulation layer, allowing the use of lower write and read voltages while maintaining effective operation of the ferroelectric capacitor, thereby preventing electrical damage to the interface insulation layer
Solution Approach 2:
The patent changes the electrical parameters by introducing a charge compensation layer with specific charge density to offset the voltage drop. This parameter change allows the system to operate at lower voltages, transforming the voltage compensation mechanism from increasing applied voltage to modifying the electric field distribution through charge injection
2Reliability
If the write voltage or read voltage is increased to compensate for the voltage drop, then the voltage drop is compensated, but charge traps are formed in the interface insulation layer or at interfaces
Solution Approach 1:
The charge compensation layer acts as an intermediary that provides voltage compensation through electric field generation rather than through high applied voltages. This intermediary mechanism prevents the formation of charge traps that would otherwise be created by excessive voltages, as the compensation is achieved through controlled charge injection into the compensation layer rather than through stress on the interface insulation layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the operating voltage, minimizes interface defects, and improves charge retention and storage capability, resulting in enhanced durability and a larger storage window for ferroelectric memories.
Implementation Method 1
Incorporating a voltage divider capacitor, either high-dielectric-constant or ferroelectric, connected in parallel with the transistor to reduce the operating voltage on the ferroelectric capacitor
Implementation Method 2
The ferroelectric memory is a memory made according to a principle that a polarization direction of a ferroelectric material changes under an action of electric field
Data Source
Figure 1a~1b
Figure 2~3
Figure 4a~4b
AI summary
This application provides a ferroelectric memory and a storage device, to reduce an operating voltage, reduce an interface defect in the ferroelectric memory, and improve durability of the ferroelectric memory. The ferroelectric memory includes at least one storage cell. Each storage cell includes a transistor, a first ferroelectric capacitor, and at least one voltage divider capacitor. The transistor includes a gate electrode, a source electrode, and a drain electrode. One electrode of the first ferroelectric capacitor is connected to the gate electrode. The other electrode of the first ferroelectric capacitor is connected to a word line. One electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the gate electrode, and the other electrode of each voltage divider capacitor in the at least one voltage divider capacitor is connected to the source electrode.