Ferroelectric Memory Wafer Bonding for High-Temperature Crystallization

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Solution Overview

Problem

The challenge in forming ferroelectric-based memory devices at the back-end-of-line (BEOL) level is achieving crystallization of ferroelectric films without damaging front-end-of-line (FEOL) structures due to thermal constraints, as excessive heat can deteriorate FEOL features.

Innovation Solution

A wafer-on-wafer process is employed to fabricate logic devices and ferroelectric memory devices separately, allowing for thermal treatment of the ferroelectric film at temperatures above 550°C without affecting FEOL structures, thereby enhancing crystallization quality and improving device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If thermal treatment is applied to grow ferroelectric films, then crystallization quality is improved, but FEOL structures are damaged due to excessive heat

Engineering Contradiction:

Improvecrystallization qualityVSAvoidthermal damage to FEOL structures

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The fabrication process is divided into two separate wafers: one for FEOL logic devices and another for ferroelectric memory structures. This segmentation allows independent thermal processing of each wafer, enabling high-temperature treatment of the ferroelectric wafer without exposing the FEOL structures to damaging heat.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A wafer-on-wafer bonding interface acts as an intermediary between the FEOL logic devices and the ferroelectric memory structures. This bonding interface isolates the two structures, allowing the ferroelectric wafer to undergo thermal treatment while the FEOL wafer remains protected from thermal damage.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If ferroelectric-based memory devices are formed at BEOL level, then integration density is improved, but thermal treatment capability is reduced

Engineering Contradiction:

Improveintegration densityVSAvoidthermal treatment capability

Core Design Contradiction:

ProductivityVSTemperature

Solution Approach 1:

The solution moves from a single-wafer vertical integration approach to a multi-wafer horizontal integration approach. By stacking multiple wafers (FEOL logic wafer + ferroelectric memory wafer) through wafer-on-wafer bonding, the system achieves high integration density while maintaining independent thermal processing capability for each wafer.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures improved crystallization of the ferroelectric film while preventing damage to FEOL structures, leading to enhanced performance of ferroelectric memory devices.

Implementation Method 1

allowing for thermal treatment of the ferroelectric film at temperatures above 550°C

Methodology Applied

Scientific EffectThermal treatment: Heat Treatment

Implementation Method 2

enhancing crystallization quality

Methodology Applied

Scientific EffectCrystallization: Crystallisation

Data Source

PatentUS20250365967A1Ferroelectric-based memory device and method of forming the same

Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method of forming a memory device according to the present disclosure includes forming a trench in a first substrate of a first wafer, depositing a data-storage element in the trench, performing a thermal treatment to the first wafer to improve a crystallization in the data-storage element, forming a first redistribution layer over the first substrate, forming a transistor in a second substrate of a second wafer, forming a second redistribution layer over the second substrate, and bonding the first wafer with the second wafer after the performing of the thermal treatment. The data-storage element is electrically coupled to the transistor through the first and second redistribution layers.