Ferroelectric Memory Wafer Bonding for High-Temperature Crystallization
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Solution Overview
Problem
The challenge in manufacturing ferroelectric-based memory devices is achieving crystallization of the ferroelectric layer without damaging the front-end-of-line (FEOL) structures, as excessive heat can deteriorate these components during thermal treatment, which is necessary for proper crystallization but often kept below 400°C to prevent damage.
Innovation Solution
The wafer-on-wafer process is used to fabricate logic devices and ferroelectric memory devices separately, allowing the ferroelectric film to undergo thermal treatment at temperatures above 550°C without subjecting the FEOL structures to excessive heat, thereby improving crystallization quality and preventing damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thermal treatment temperature is increased to improve crystallization quality, then crystallization quality improves, but FEOL structures are damaged
Solution Approach 1:
The patent divides the device structure into two separate wafers: a first wafer containing the FEOL structures and a second wafer containing the ferroelectric memory structures. This segmentation allows independent thermal treatment of each wafer, enabling high-temperature crystallization (above 550°C) on the second wafer without exposing the temperature-sensitive FEOL structures on the first wafer to damaging heat.
Solution Approach 2:
The patent introduces an intermediary bonding interface between the first wafer and second wafer. The wafers are bonded together through this interface, allowing the ferroelectric layer on the second wafer to be thermally treated at high temperatures while the FEOL structures on the first wafer remain protected. The bonding interface acts as a mediator that enables thermal isolation between the two structure sets.
2Reliability
If thermal treatment temperature is kept low to protect FEOL structures, then FEOL structures are protected, but crystallization quality is insufficient
Solution Approach 1:
By segmenting the device into two separate wafers that can be independently processed, the patent enables the second wafer to undergo high-temperature thermal treatment (above 550°C) sufficient for high-quality crystallization of the ferroelectric layer, while the first wafer with FEOL structures undergoes separate, lower-temperature processing to maintain structural integrity.
Solution Approach 2:
The patent transitions from a single-plane processing approach to a three-dimensional stacked architecture where the first wafer and second wafer are bonded together. This vertical stacking in another dimension allows simultaneous optimization of thermal processing conditions for both FEOL structures and ferroelectric memory structures.
3Manufacturing precision
If wafer-on-wafer process is used to enable high-temperature treatment, then crystallization quality improves, but device complexity increases
Solution Approach 1:
The patent segments the fabrication process into separate processing streams for the first wafer and second wafer, allowing each to be optimized independently. The first wafer undergoes standard FEOL processing, while the second wafer undergoes specialized high-temperature crystallization processing, reducing overall process complexity compared to attempting to process both structures together.
Solution Approach 2:
The patent performs preliminary bonding of the first and second wafers before final device assembly. This preliminary action enables subsequent high-temperature thermal treatment of the second wafer to be performed without affecting the FEOL structures, as the bonding is already established and can withstand the thermal process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of ferroelectric memory devices by ensuring high-quality crystallization of the ferroelectric layer while protecting the FEOL structures from thermal damage, leading to improved device performance with increased reliability.
Implementation Method 1
the ferroelectric film to undergo thermal treatment at temperatures above 550°C
Implementation Method 2
achieving crystallization of the ferroelectric layer
Data Source
AI summary
A method of forming a memory device according to the present disclosure includes forming a trench in a first substrate of a first wafer, depositing a data-storage element in the trench, performing a thermal treatment to the first wafer to improve a crystallization in the data-storage element, forming a first redistribution layer over the first substrate, forming a transistor in a second substrate of a second wafer, forming a second redistribution layer over the second substrate, and bonding the first wafer with the second wafer after the performing of the thermal treatment. The data-storage element is electrically coupled to the transistor through the first and second redistribution layers.