Ferroelectric MFMIS-FET with Segmented Top Electrode
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Solution Overview
Problem
The existing MFMIS-FET structures face limitations in tuning the thicknesses and dielectric constants of ferroelectric and gate insulation layers, affecting the capacitance ratio and thus the applicability and endurance of nonvolatile memory devices.
Innovation Solution
The use of a semiconductor structure with a ferroelectric material like hafnium dioxide, where the top electrode has a smaller projected area than the floating gate electrode, allowing for separate scaling of capacitors and improved electric field distribution, enhancing the endurance of MFMIS-FET devices through gate-last and gate-first integration schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thicknesses and dielectric constants of ferroelectric and gate insulation layers are tuned to optimize capacitance ratio, then the applicability and endurance of nonvolatile memory devices are improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent applies parameter changes by systematically varying the thicknesses of the ferroelectric layer (e.g., 5-20 nm) and gate insulation layer (e.g., 2-10 nm) to optimize the capacitance ratio. It also changes dielectric constants by selecting different materials (e.g., hafnium dioxide with high dielectric constant for ferroelectric layer, silicon dioxide for gate insulation layer), thereby achieving optimal capacitance ratios that improve device endurance without requiring overly complex structures.
Solution Approach 2:
The patent employs composite materials by combining ferroelectric materials (such as hafnium dioxide, lead zirconate titanate) with gate insulation materials (such as silicon dioxide, silicon oxynitride) to create a multi-layer gate structure. This composite approach enables independent optimization of each layer's properties, achieving the desired capacitance ratio while maintaining manufacturability and device reliability.
2Use of energy by moving object
If the capacitance ratio between the first capacitor (ferroelectric layer) and second capacitor (gate insulation layer) is optimized, then the bias voltage required for applying external electric field is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent reduces bias voltage requirements by optimizing the capacitance ratio through parameter changes in layer thicknesses. By setting the ferroelectric layer thickness to 5-20 nm and gate insulation layer thickness to 2-10 nm, the capacitance ratio is tuned to minimize the bias voltage needed for switching. This parameter optimization achieves lower energy consumption while the thickness ranges are selected to be compatible with standard semiconductor manufacturing capabilities.
Solution Approach 2:
The patent adopts a practical approach by selecting thickness parameters that can be achieved with conventional manufacturing tolerances, rather than pursuing theoretically optimal but unmanufacturable precision. The specified thickness ranges account for typical process variations, ensuring that the optimized capacitance ratio can be achieved in production without requiring excessive manufacturing precision that would increase costs and complexity.
3Adaptability or versatility
If the top electrode has a smaller projected area than the floating gate electrode, then the electric field distribution is improved and device scalability is enhanced, but the device complexity increases due to additional patterning steps
Solution Approach 1:
The patent applies segmentation by dividing the electrode structure into two distinct components: a floating gate electrode and a top electrode with different projected areas. The top electrode is patterned to be smaller than the floating gate electrode, creating a segmented structure that improves electric field confinement and distribution. This segmentation enables better control over the electric field profile, enhancing device scalability to smaller technology nodes.
Solution Approach 2:
The patent addresses the area relationship between electrodes by introducing a dimensional consideration in the vertical stacking configuration. The top electrode is positioned above the floating gate electrode in the vertical dimension, with its projected area intentionally made smaller. This dimensional arrangement in the vertical stack allows for improved electric field distribution while the patterning is achieved through standard photolithography and etching processes, making the increased complexity manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the voltage required for applying an external electric field, improving the endurance and scalability of MFMIS-FET devices, particularly down to the 28 nm technology node, by optimizing the capacitance ratio and electric field distribution.
Implementation Method 1
Ferroelectric materials can maintain an electric polarization in the absence of an external electrical field
Implementation Method 2
The remanent polarization of the ferroelectric layer can have an influence on the electrical conductivity of the channel region
Implementation Method 3
A first capacitor is provided by the upper and lower electrodes, with the ferroelectric layer arranged as a capacitor dielectric therebetween
Data Source
AI summary
An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.