Ferroelectric Multiplier Cell With Sequential Reset for Low Power
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Solution Overview
Problem
Conventional multiplier cells in CMOS logic require numerous transistors, leading to increased power consumption and area, which poses a challenge in achieving lower power consumption and compact design, especially in battery-powered devices.
Innovation Solution
The use of non-linear polar materials such as ferroelectric or paraelectric materials in majority and minority gates, combined with a transmission-gate based reset mechanism, reduces the number of transistors and interconnects, enabling more compact and power-efficient multiplier circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CMOS logic gates (AND, OR, XOR) are used to build multiplier cells, then the logic functions are accurate and reliable, but the number of transistors increases, leading to increased power consumption and area
Solution Approach 1:
The patent changes the material parameter from conventional CMOS dielectric to ferroelectric material, which exhibits non-linear polarization characteristics. This material parameter change enables the circuit to achieve the same logic functions with fewer transistors, thereby reducing power consumption while maintaining reliability
Solution Approach 2:
The patent employs a composite structure combining ferroelectric material with CMOS transistors. The ferroelectric layer is integrated into the capacitor structure of the logic gates, creating a hybrid system that leverages both the switching capability of CMOS and the non-linear polarization properties of ferroelectric materials to reduce power consumption
2Reliability
If conventional CMOS logic gates are used to build multiplier cells, then the logic functions are accurate, but the number of transistors increases, leading to increased area
Solution Approach 1:
By changing the dielectric material parameter to ferroelectric material with non-linear polarization characteristics, the patent reduces the number of transistors required per logic gate from six (conventional CMOS) to fewer, directly reducing the circuit area while maintaining logic function accuracy
Solution Approach 2:
The patent extracts and removes redundant transistors from the conventional CMOS gate structure by utilizing the non-linear polarization properties of ferroelectric material to achieve the same logic functionality with a reduced transistor count, thereby reducing area
3Productivity
If conventional CMOS logic is used, then the circuit operates continuously, but power consumption increases, especially in battery-powered devices
Solution Approach 1:
The patent implements periodic reset action using transmission gates controlled by reset signals. The circuit operates in periodic cycles of computation followed by reset phases, during which the ferroelectric capacitors are discharged. This periodic operation allows the circuit to maintain functionality while reducing average power consumption compared to continuous operation
Solution Approach 2:
The ferroelectric material provides self-retention of state without continuous power supply. The non-linear polarization characteristics allow the circuit to maintain its state automatically, eliminating the need for continuous refreshing or powering, thus enabling intermittent operation with zero power drain when not in use
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly reduced power consumption, compact circuitry, and the ability to operate at lower voltage levels, with the non-linear polar materials allowing for intermittent operation and zero power drain when not in use, while maintaining accurate logic functions.
Implementation Method 1
The capacitors may comprise non-linear polar material, such as, but not limited to, ferroelectric material
Implementation Method 2
The capacitors may comprise non-linear polar material, such as, but not limited to, ferroelectric material
Implementation Method 3
a transmission-gate based reset mechanism
Data Source
AI summary
A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.