Ferroelectric Negative Capacitance Interconnect for DRAM
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Solution Overview
Problem
The integration of new materials in interconnect structures for high-speed integrated circuits, such as DRAM memory cells, faces a conflict between the need for reduced vertical capacitance for faster device operation and increased storage capacity, as ultra-low-k dielectrics used to minimize capacitance lack structural integrity and are porous, while ferroelectric capacitors offer non-linear capacitance that can enhance storage capacity but are unstable.
Innovation Solution
The use of ferroelectric capacitors with negative capacitance coupled in series with conventional dielectric capacitors within the interconnect structure, forming a bi-layer configuration that stabilizes the negative capacitor and allows for tuning of overall capacitance to achieve high capacity DRAM memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ultra-low-k dielectrics are used to minimize vertical capacitance, then device operation speed is improved, but structural integrity deteriorates and porosity increases
Solution Approach 1:
The patent uses a composite interconnect structure combining copper interconnect lines with ultra-low-k dielectric material (porous silicon oxide) for insulation. This composite approach allows the system to benefit from the low capacitance properties of ULK while maintaining structural integrity through the copper framework and optimized dielectric composition, resolving the contradiction between speed improvement and structural stability
2Quantity of substance
If conventional dielectric capacitors are used, then structural stability is maintained, but storage capacity is insufficient for high-density memory
Solution Approach 1:
The patent changes the fundamental parameter of capacitance behavior by transitioning from linear dielectric capacitors to ferroelectric capacitors with non-linear capacitance characteristics. This parameter change enables much higher storage capacity per unit area while the ferroelectric material's properties allow for fast switching speeds, simultaneously improving both storage capacity and maintaining productivity
3Quantity of substance
If ferroelectric capacitors are used to increase storage capacity, then storage capacity is improved, but stability deteriorates due to negative capacitance region
Solution Approach 1:
The patent introduces a thin dielectric layer as an intermediary between the ferroelectric capacitor and the read/write circuitry. This dielectric intermediary stabilizes the ferroelectric capacitor by preventing it from operating in the unstable negative capacitance region, while still allowing the ferroelectric material to provide its high storage capacity benefits. The dielectric acts as a mediator that enables reliable operation of the high-capacity ferroelectric device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration provides a large, tunable capacitance value, overcoming the scaling limitations and achieving high storage capacity while maintaining fast device operation, by leveraging the non-linear properties of ferroelectric materials to enhance storage capacity without compromising speed.
Implementation Method 1
At certain temperatures, ferroelectric materials exhibit spontaneous polarization P that can be reversed by applying an electric field
Implementation Method 2
the relationship between the polarization P and the applied electric field E of a ferroelectric capacitor exhibits hysteresis and is therefore non-linear
Implementation Method 3
When a voltage is applied across the plates, dipole moments within the dielectric material align to produce an internal polarization P that opposes the electric field E associated with the applied voltage
Implementation Method 4
The amount of charge stored on the plates is proportional to the applied voltage, according to the linear relationship Q=CV
Data Source
AI summary
An interconnect structure for use in coupling transistors in an integrated circuit is disclosed, including various configurations in which ferroelectric capacitors exhibiting negative capacitance are coupled in series with dielectric capacitors. In one embodiment, the negative capacitor includes a dielectric/ferroelectric bi-layer. When a negative capacitor is electrically coupled in series with a conventional dielectric capacitor, the series combination behaves like a stable ferroelectric capacitor for which the overall capacitance can be measured experimentally, and tuned to a desired value. The composite capacitance of a dielectric capacitor and a ferroelectric capacitor having negative capacitance coupled in series is, in theory, infinite, and in practice, very large. A series combination of positive and negative capacitors within a microelectronic interconnect structure can be used to make high capacity DRAM memory cells.