Ferroelectric Layer Negative Capacitance Non-Volatile Memory
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Solution Overview
Problem
Non-volatile memory devices require high voltage operations for programming and erasing, leading to high power consumption and increased manufacturing costs due to the need for high voltage MOS devices and additional complex processes.
Innovation Solution
A ferroelectric layer is disposed between the gate stack structure and the erase gate structure to create a negative capacitance effect, reducing the required applied voltage and eliminating the need for high voltage MOS devices by amplifying the voltage applied to the erase gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage operations are used for programming and erasing, then memory device functionality is achieved, but power consumption increases
Solution Approach 1:
The patent introduces a ferroelectric layer that changes the electrical parameters of the gate structure, enabling voltage amplification through negative capacitance effect. This allows the system to achieve the same memory functionality with lower applied voltages, directly reducing power consumption while maintaining reliable operation
Solution Approach 2:
The ferroelectric layer acts as an intermediary between the control gate and the channel, providing voltage amplification. This mediator enables the system to achieve high electric fields in the channel (necessary for memory operation) while applying lower voltages to the control gate, thus reducing power consumption
2Reliability
If high voltage MOS devices are used, then high voltage operations are achieved, but manufacturing cost increases
Solution Approach 1:
The ferroelectric layer fundamentally changes the electrical parameters of the MOS structure, providing voltage amplification that eliminates the need for specialized high voltage MOS devices. Standard low-voltage MOS devices can be used instead, simplifying manufacturing and reducing costs while maintaining the ability to perform high voltage operations through the amplification effect
Solution Approach 2:
The ferroelectric layer serves as an intermediary that provides the voltage amplification function previously requiring specialized high voltage devices. This allows standard MOS devices to be used in conjunction with the ferroelectric layer to achieve high voltage operations, thereby reducing manufacturing complexity and cost
3Reliability
If additional processes for forming high voltage MOS devices are implemented, then high voltage operations are achieved, but device complexity increases
Solution Approach 1:
The introduction of the ferroelectric layer changes the operational parameters of standard MOS devices, enabling them to function in high voltage regimes through voltage amplification. This approach avoids the need for additional processing steps required to create specialized high voltage MOS devices, thereby reducing device complexity while maintaining high voltage capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, simplifies the manufacturing process, and lowers costs by allowing lower voltage operations while maintaining effective memory device functionality.
Implementation Method 1
A ferroelectric layer is disposed between the gate stack structure and the erase gate structure to create a negative capacitance effect, reducing the required applied voltage by amplifying the voltage applied to the erase gate structure
Data Source
AI summary
A non-volatile memory device includes a substrate, a gate stack structure, an erase gate structure, and a ferroelectric layer. The gate stack structure is disposed on the substrate. The erase gate structure is disposed on the substrate and disposed at a first side of the gate stack structure. The ferroelectric layer is disposed on a sidewall of the gate stack structure, and the ferroelectric layer is disposed between the gate stack structure and the erase gate structure. The ferroelectric layer disposed between the gate stack structure and the erase gate structure may be used to forma negative capacitance effect for amplifying the voltage applied to the erase gate structure. The purpose of reducing power consumption may be achieved accordingly.