Ferroelectric Oxide Semiconductor Stack With Shared Electrode Layout

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Solution Overview

Problem

Current semiconductor devices face challenges in achieving high integration and low-power driving due to the need for separate terminals between ferroelectric and semiconductor layers, limiting their compactness and operational efficiency.

Innovation Solution

A semiconductor device configuration that includes a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer between two electrodes, where the conductive metal oxide layer controls the crystal direction of the ferroelectric layer without preventing electric current flow, and the ferroelectric layer controls polarization direction to form depletion or accumulation regions in the semiconductor layer, enabling variable resistance and efficient information storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If separate terminals are used between ferroelectric and semiconductor layers, then device functionality is maintained, but device complexity and area increase

Engineering Contradiction:
Improvestructure complexityVSAvoiddevice functionality
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent merges the terminal structure by making the second electrode common to both the ferroelectric layer and the semiconductor layer. This eliminates the need for separate terminals, reducing device complexity and area while maintaining proper electrical connections and functionality through the shared electrode architecture.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The second electrode serves multiple functions simultaneously: it acts as the bottom electrode for the ferroelectric layer and the top electrode for the semiconductor layer. This multi-functional design reduces the total number of terminals required while ensuring both components operate correctly with appropriate electrical connections.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If device size is reduced for high integration, then integration density increases, but manufacturing precision requirements increase

Engineering Contradiction:
Improveintegration densityVSAvoidlayer alignment precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

By merging the terminal structures and using a shared second electrode, the patent reduces the overall device footprint. This compact design increases integration density while the simplified structure actually reduces alignment complexity compared to separate terminal configurations, as fewer layers require precise stacking.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If conductive metal oxide layer is added to control crystal direction, then ferroelectric layer performance improves, but device complexity increases

Engineering Contradiction:
Improveferroelectric performanceVSAvoidlayer structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive metal oxide layer serves as an intermediary between the ferroelectric layer and the electrode, mediating the crystal orientation through epitaxial growth. This thin intermediate layer enables precise control of ferroelectric crystal direction without requiring complex structural modifications, as it simply provides the necessary lattice template for oriented growth.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for increased integration, low-power driving, and improved compactness of semiconductor devices by eliminating the need for separate terminals between the ferroelectric and semiconductor layers, enhancing operational efficiency and miniaturization.

Implementation Method 1

The semiconductor device may be configured to control a polarization direction of a polarization of the ferroelectric layer according to a direction of an electric field formed between the first electrode and the second electrode. The semiconductor device may be further configured to form a depletion region or an accumulation region in the semiconductor layer according to the polarization direction of the polarization of the ferroelectric layer.

Methodology Applied
Scientific EffectPolarization: Polarisation

Implementation Method 2

The conductive metal oxide layer may have a crystal direction that is the same as or similar to a desired crystal direction of the ferroelectric layer. A difference in lattice constant between the ferroelectric layer and the conductive metal oxide layer may be relatively small.

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS20240266445A1Semiconductor device
Publication Date: 2024.08.08 SAMSUNG ELECTRONICS CO LTD
  • US20240266445A1 patent drawing
  • US20240266445A1 patent drawing
  • US20240266445A1 patent drawing

AI summary

A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.