Ferroelectric Pillar Capacitor Memory for Low-Voltage High Density
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Solution Overview
Problem
Existing volatile memories, such as SRAM and DRAM, suffer from high power consumption and low density, making them unsuitable for low-power and compact computing devices, while non-volatile memories like MRAM, NAND, and NOR flash face challenges with high write energy and low density.
Innovation Solution
A 1T-1C memory bit-cell design utilizing a pillar capacitor with ferroelectric material and conductive oxides as electrodes, where one conductive oxide layer wraps around the pillar, allowing for low voltage switching and high density by integrating with planar or non-planar transistors, both frontend and backend.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memories (SRAM/DRAM) are used, then fast access speed is achieved, but power consumption increases and density decreases
Solution Approach 1:
The patent changes the operational voltage parameter by implementing a unidirectional bit-line that maintains voltage in a single direction, enabling low-voltage operation of the capacitor-based memory cell while maintaining fast access speeds comparable to volatile memories
Solution Approach 2:
The patent transitions from planar memory structures to three-dimensional capacitor structures with vertical stacking, increasing storage density without compromising access speed by utilizing the vertical dimension for additional storage capacity
2Duration of action of stationary object
If non-volatile memories (MRAM/NAND/NOR flash) are used, then data retention is improved, but write energy increases and density decreases
Solution Approach 1:
The patent replaces the complex write mechanisms of MRAM (magnetic field generation) and flash (high-voltage tunneling) with a simpler capacitor charging/discharging mechanism that requires significantly less write energy while maintaining non-volatile data retention through the ferroelectric or phase-change material in the capacitor
Solution Approach 2:
The patent reduces the write voltage parameter from the high voltages required by traditional non-volatile memories to low voltages suitable for capacitor-based operation, thereby reducing write energy consumption while maintaining data retention through the inherent non-volatility of the capacitor material
3Quantity of substance
If memory density is increased, then more bit-cells per die are achieved, but device complexity increases
Solution Approach 1:
The patent segments the memory system into distinct functional components: a unidirectional bit-line network for address decoding and a capacitor array for storage, allowing independent optimization of each segment and simplifying the overall design while achieving high density through systematic scaling
Solution Approach 2:
The unidirectional bit-line structure serves multiple functions simultaneously: it acts as an address line for selecting memory cells, a data line for reading/writing, and a voltage supply line, thereby reducing the number of separate components needed and simplifying the device architecture while increasing density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves high-density, low-voltage non-volatile memory operation with reduced power consumption, enabling more bit-cells per die and maintaining non-volatility.
Implementation Method 1
a capacitive structure adjacent to one of the source or drain of the transistor, wherein the capacitive structure comprises: a first structure comprising refractive inter-metallic, a second structure comprising a first conductive oxide, a third structure comprising a perovskite, and a fourth structure comprising a second conductive oxide
Data Source
AI summary
Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.