Ferroelectric Random Access Memory Voltage Control
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Solution Overview
Problem
Conventional ferroelectric random access memory devices face high power consumption during read/write operations and require multiple voltage levels, including negative voltages, which complicates the configuration and increases the risk of write disturbance and integration issues.
Innovation Solution
A ferroelectric random access memory device with a memory cell array comprising one ferroelectric transistor (FeFET) connected between read and source lines, and a transistor between the bit line and the FeFET gate, using a read/write control unit to apply pre-designated positive and ground voltages to perform read/write operations without negative voltages, shifting the hysteresis curve to achieve reduced power consumption and simplified voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional read/write methods are used in 1 FeFET, 1T+1FeFET, or 2T+1FeFET structures, then data can be stored and retrieved, but power consumption is large during read/write operations
Solution Approach 1:
The patent changes the voltage parameters from conventional multi-level (including negative voltages) to a simplified two-level system using only ground voltage and a first voltage level. This parameter change reduces power consumption while maintaining reliable read/write operations through the modified cell structure and operating method
2Ease of manufacture
If conventional read/write methods are used, then data can be written to memory cells, but the method requires using negative voltage which complicates the configuration
Solution Approach 1:
The patent eliminates negative voltage requirements by changing the voltage parameters to only ground and first voltage levels. This simplifies the power supply configuration and manufacturing while maintaining full write operation capability through the modified cell structure that uses ground voltage on bit lines during write operations
3Device complexity
If 1 FeFET structure is used to achieve small cell size and high integration, then degree of integration is improved, but write disturbance may occur
Solution Approach 1:
The patent applies different voltage conditions to different parts of the memory cell during write operations. By applying ground voltage specifically to the bit line connected to the FeFET gate while maintaining appropriate voltages on other lines, the invention achieves localized control that prevents write disturbance in adjacent cells while maintaining high integration density
4Reliability
If 1T+1FeFET or 2T+1FeFET structures are used to prevent write disturbance, then write disturbance is reduced, but threshold voltage drop may occur and cell area increases
Solution Approach 1:
The patent changes the voltage parameters applied during read operations to prevent threshold voltage drop. By carefully controlling the voltage levels and timing in the modified cell structure, the invention maintains stable threshold voltages without requiring larger cell areas or additional transistors
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables read/write operations with fewer voltage levels, reduces power consumption, and eliminates the need for negative voltages, improving integration and simplifying the power supply configuration while minimizing write disturbance.
Implementation Method 1
the threshold voltage (VTH) varies depending on the gate-source voltage (VGS) or the gate-drain voltage (VGD) according to the hysteresis characteristic of the ferroelectric
Implementation Method 2
a ferroelectric random access memory device that uses a ferroelectric as a memory element
Data Source
AI summary
A ferroelectric random access memory device comprises: a memory cell array including a plurality of memory cells each having one ferroelectric transistor (FeFET) connected between a read line of a plurality of read lines and a source line of a plurality of source lines and one transistor connected between a bit line of a plurality of bit lines and a gate of the FeFET and having a gate connected to a corresponding word line of a plurality of word lines; and a read/write control unit, when address information for a memory cell to be written is applied with a write command and data, selecting a word line and a read line corresponding to a row address and applying a write voltage having a positive voltage level, and applying a ground voltage to the selected read line, and applying the write voltage to a bit line corresponding to a memory cell.