Ferroelectric Memory Readout Below Coercive Voltage for CiM Reuse

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Solution Overview

Problem

Memory states in memory devices are destroyed during read operations, and the memory states for each memory cell cannot be identified after compute-in-memory (CiM) operations, leading to loss of memory states corresponding to CiM weights.

Innovation Solution

Implementing a read operation with a read voltage level below the coercive voltage level to prevent destruction of memory states, allowing for non-destructive read and enabling the reuse of memory states for subsequent CiM operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a read operation is performed with voltage above the coercive voltage level, then the read operation can be completed, but the memory state is destroyed

Engineering Contradiction:
Improveread operation completionVSAvoidmemory state destruction
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent changes the voltage parameter of the read operation from above the coercive voltage level to below the coercive voltage level. This parameter change allows the read operation to sense the memory state without causing polarization switching, thereby preventing memory state destruction while maintaining read operation functionality

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies partial action by using a voltage level that is sufficient to sense the memory state but insufficient to cause polarization switching. The read voltage is deliberately kept below the coercive voltage level, applying only the necessary amount of voltage to achieve reading without the excessive voltage that would destroy the memory state

Inventive Principle:
Principle #16Partial or excessive action

2Productivity

If charge sharing is performed for CiM operation, then computing can be done in memory, but the memory state for each memory cell cannot be identified

Engineering Contradiction:
Improvecompute-in-memory operationVSAvoidmemory state loss
Core Design Contradiction:
ProductivityVSLoss of information

Solution Approach 1:

The patent performs preliminary sensing of the memory state before the CiM operation causes complete charge sharing. By reading the memory state at a voltage level below the coercive voltage level before the CiM operation, the system captures the initial memory state information that would otherwise be lost during charge sharing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates a copy of the memory state information by sensing it at a safe voltage level before the CiM operation. This copied information is preserved separately and can be used after the CiM operation without needing to reconstruct the original memory state from the charge-shared result

Inventive Principle:
Principle #26Copying

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Preserves memory states after read operations, enabling their reuse in subsequent CiM operations without loss, thereby enhancing the efficiency and reliability of memory devices.

Implementation Method 1

Each of the memory elements is a ferroelectric capacitor... storing a data bit... polarization of the memory element

Methodology Applied
Scientific EffectPolarization: Polarisation

Implementation Method 2

charge sharing... the memory states corresponding to CiM weights are loss after CiM computing

Methodology Applied
Scientific EffectCharge sharing: Capacitance

Data Source

PatentUS20250322886A1Memory device and operating method thereof
Publication Date: 2025.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250322886A1 patent drawing
  • US20250322886A1 patent drawing
  • US20250322886A1 patent drawing

AI summary

A method includes: charging a bit line to a read voltage level; coupling the bit line to a memory element; and adjusting a voltage level of the bit line from the read voltage level according to a data bit stored in the memory element. The read voltage level is smaller than a coercive voltage level of the memory element.