Ferroelectric Memory Reference Generation Without Reference Cells
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Solution Overview
Problem
Ferroelectric memory devices with 1T1C architecture face challenges in generating a reference voltage to differentiate cell information, which is crucial for sensing and writing operations, due to the need for additional pairs of reference cells and large die size considerations.
Innovation Solution
A method involving a unity gain buffer and balancing capacitor is used to generate a reference voltage, allowing identical capacitance between data and reference bit-lines, and a local sense amplifier to amplify signals to rail-to-rail supply voltages, reducing die size and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional pairs of reference cells are used to generate reference voltage, then sensing and writing operations can be performed, but die size increases
Solution Approach 1:
The patent extracts the reference voltage generation function from traditional reference cells and relocates it to the bit-line structure itself. By using the local bit-line as the reference voltage source and removing dedicated reference cells, the design eliminates the need for additional reference cell pairs while maintaining sensing accuracy, thereby reducing die size.
Solution Approach 2:
The local bit-line serves multiple functions: it acts as both a data transmission line and a reference voltage source. This multi-functionality eliminates the need for separate reference cells, reducing the number of components required while maintaining the ability to perform sensing and writing operations.
2Measurement precision
If local sense amplifier amplifies signal to rail-to-rail supply voltages, then signal accuracy improves, but power consumption increases
Solution Approach 1:
The local sense amplifier performs preliminary amplification of the signal to rail-to-rail supply voltages before transmission to global bit-lines. This preliminary action ensures that the signal is fully amplified and standardized early in the signal path, improving measurement precision while allowing subsequent stages to operate with lower power requirements.
Data Source
AI summary
A FRAM memory device can include a plurality of FRAM memory cells, each FRAM memory cell including one transistor and one capacitor electric-ally coupled to the at least one transistor. The capacitor can be configured to store a bit of data. The memory device can also include a local bit-line configured to carry data to be written to the plurality of memory cells. The memory device can further include a global bit-line configured to communicate with the local bit-line to carry the data to be written to the plurality of memory cells. The memory device can additionally include a local sense amplifier configured to amplify a signal from the global bit-line and to transfer the amplified signal to the local bit-line based on a reference signal. The local sense amplifier can be configured to generate the amplified signal based on comparison to the reference signal.