Ferroelectric Reset Transistor for Image Sensor Lag and Power Reduction
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Solution Overview
Problem
Existing image sensors face issues with image lag and signal-to-noise ratio (SNR) deterioration due to incomplete removal of photocharges from the floating diffusion node, and increased power consumption from continuous reset signal application.
Innovation Solution
Incorporating a reset transistor with a memory gate that utilizes a ferroelectric gate dielectric layer with spontaneous polarization characteristics, allowing the reset transistor to maintain a turn-on or turn-off state without external stimulus, and controlling its state with specific reset pulses to optimize operation during integration sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset transistor is continuously operated to remove photocharges from the floating diffusion node, then image lag is reduced, but power consumption increases
Solution Approach 1:
The reset transistor is operated periodically rather than continuously. A reset pulse is applied only during specific periods (when photocharges need to be removed), allowing the transistor to remain in a low-power state during other periods when photocharge accumulation is not occurring. This periodic operation maintains image lag reduction while significantly reducing overall power consumption.
2Reliability
If the reset transistor is continuously activated to prevent voltage level changes at the floating diffusion node, then SNR characteristics improve, but power consumption increases
Solution Approach 1:
The reset transistor is activated periodically to maintain voltage stability at the floating diffusion node only when needed for SNR optimization, rather than maintaining continuous activation. This approach preserves signal-to-noise ratio characteristics while reducing the power consumption associated with continuous transistor operation.
3Reliability
If the reset transistor operates with precise timing control using memory gate, then photocharge removal completeness improves, but device complexity increases
Solution Approach 1:
The memory gate utilizes ferroelectric material properties (spontaneous polarization) to maintain transistor state without continuous external control. By changing the polarization state of the ferroelectric layer through voltage pulses, the transistor can be precisely controlled to achieve complete photocharge removal while reducing the complexity of continuous control circuitry.
Solution Approach 2:
The memory gate with ferroelectric material provides self-maintaining state capability. Once a voltage pulse sets the desired state, the ferroelectric polarization maintains it without requiring continuous external control signals, thereby reducing device complexity while ensuring precise and complete photocharge removal when activated.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves image lag and SNR characteristics while reducing power consumption by ensuring complete photocharge removal and preventing voltage level changes at the floating diffusion node, thereby minimizing noise and leakage.
Implementation Method 1
the gate dielectric layer may include a ferroelectric substance having spontaneous polarization characteristics
Implementation Method 2
a gate dielectric layer having spontaneous polarization characteristics, where a direction of spontaneous polarization of the gate dielectric layer is changed based on the reset signal
Data Source
AI summary
An image sensor includes a photoelectric conversion element suitable for generating photocharges corresponding to incident light, a transfer transistor suitable for transferring the generated photocharges to a floating diffusion node based on a transfer signal, and a reset transistor suitable for resetting the floating diffusion node based on a reset signal and including a memory gate.


