Ferroelectric and Resistive Memory Cell for Multi-Level Storage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current nonvolatile memory devices lack the capability to efficiently store multi-level signals due to limitations in resistance and polarization states, which restricts their data storage capacity and complexity.

Innovation Solution

A nonvolatile memory device incorporating a ferroelectric memory element with a field effect transistor and a resistive memory element, where the ferroelectric memory element uses a ferroelectric gate dielectric layer to store remanent polarization, and the resistive memory element utilizes a resistance change memory layer to store resistance states, allowing for independent control and combination of these states to achieve multi-level signal storage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single memory element (ferroelectric or resistive) is used, then the device structure is simple, but the data storage capacity and signal levels are limited

Engineering Contradiction:
Improvememory element structureVSAvoiddata storage capacity
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent combines a ferroelectric memory element and a resistive memory element into a single memory cell to achieve multi-level signal storage. The ferroelectric element provides remanent polarization states while the resistive element provides resistance states, and their combination enables storage of multiple signal levels (e.g., 4-level or 8-level signals) beyond what either element could achieve alone.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If resistance and polarization states are independently controlled, then multi-level signal storage is achieved, but the control mechanism becomes complex

Engineering Contradiction:
Improvesignal storage capabilityVSAvoidcontrol mechanism
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory cell structure is designed to perform multiple functions: the ferroelectric element stores remanent polarization information, the resistive element stores resistance state information, and their combination enables multi-level signal storage. This multi-functional design allows a single memory cell to achieve complex storage capabilities without requiring separate dedicated structures for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the storage of multiple signal levels by independently controlling the remanent polarization and resistance states, thereby enhancing the data storage capacity and complexity of the memory device.

Implementation Method 1

The ferroelectric memory element includes a field effect transistor having a ferroelectric gate dielectric layer

Methodology Applied
Scientific EffectFerroelectricity:

Implementation Method 2

in a resistive memory device, an electrical resistance of an internal memory element can be reversibly changed when an external voltage or current is applied

Methodology Applied
Scientific EffectResistive switching: Electrical Resistance

Data Source

PatentUS10497433B2Nonvolatile memory device including ferroelectric memory element and resistive memory element, and method of operating nonvolatile memory device
Publication Date: 2019.12.03 SK HYNIX INC
  • US10497433B2 patent drawing
  • US10497433B2 patent drawing
  • US10497433B2 patent drawing

AI summary

A nonvolatile memory device according to one embodiment includes a ferroelectric memory element and a resistive memory element. The ferroelectric memory element includes a field effect transistor having a ferroelectric gate dielectric layer. The resistive memory element includes a resistance change memory layer disposed between a first memory electrode and a second memory electrode. A drain electrode of the field effect transistor is connected to the first memory electrode or second memory electrodes.