Ferroelectric Semiconductor Stack for Memory Window and Charge Trap Control

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving a large memory window and improved operational reliability due to limitations in the threshold voltage control and charge trapping mechanisms.

Innovation Solution

The semiconductor device incorporates a channel layer with a semiconductor material, a ferroelectric layer, a gate electrode, a first insertion layer with a low dielectric constant paraelectric material, and a second insertion layer with a high dielectric constant paraelectric material. This configuration enhances the memory window by controlling charge trapping and threshold voltage variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a ferroelectric layer is used to achieve threshold voltage control, then memory window is improved, but operational reliability deteriorates due to charge trapping limitations

Engineering Contradiction:

Improvememory windowVSAvoidoperational reliability

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent employs a composite structure consisting of a ferroelectric layer combined with two paraelectric insertion layers having different dielectric constants. This composite material approach allows the device to simultaneously achieve large memory window (through ferroelectric polarization) and improved operational reliability (through controlled charge trapping in the paraelectric layers), resolving the contradiction between these two parameters.

Inventive Principle:

Principle #40Composite materials

Solution Approach 2:

The paraelectric insertion layers act as intermediary elements between the ferroelectric layer and the electrodes. These intermediary layers with different dielectric constants facilitate controlled charge trapping and electric field distribution, enabling both large memory window and high operational reliability by mediating the interaction between the ferroelectric layer and external electric fields.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Measurement precision

If conventional insertion layers are used, then device complexity is reduced, but memory window and charge trapping control are insufficient

Engineering Contradiction:

Improvememory windowVSAvoidinsertion layer structure

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by using two different paraelectric materials with distinct dielectric constants (first paraelectric material with lower dielectric constant, second paraelectric material with higher dielectric constant) in different insertion layers. Each layer is optimized for its specific function: the first insertion layer provides baseline charge trapping, while the second insertion layer enhances electric field control. This localized optimization achieves superior memory window without excessive overall complexity.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed semiconductor device structure significantly increases the memory window and improves operational reliability by effectively managing charge traps and threshold voltage changes, leading to enhanced performance in memory devices.

Implementation Method 1

Ferroelectrics are materials having ferroelectricity in which internal electric dipole moments are aligned to maintain spontaneous polarization even when an electric field is no longer being applied thereto from the outside.

Methodology Applied

Scientific EffectFerroelectricity:

Implementation Method 2

a first insertion layer between the ferroelectric layer and the gate electrode and including a first paraelectric material, and a second insertion layer arranged between the channel layer and the ferroelectric layer, the second insertion layer including a second paraelectric material having a dielectric constant higher than a dielectric constant of the first paraelectric material

Methodology Applied

Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS20250126875A1Semiconductor device and electronic device including the same

Publication Date: 2025.04.17 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided is a semiconductor device including a channel layer including a semiconductor material, a ferroelectric layer arranged on the channel layer and including a ferroelectric material, a gate electrode arranged on the ferroelectric layer, a first insertion layer arranged between the ferroelectric layer and the gate electrode and including a first paraelectric material, and a second insertion layer arranged between the channel layer and the ferroelectric layer and including a second paraelectric material having a dielectric constant higher than a dielectric constant of the first paraelectric material.