Ferroelectric Storage Layer Layout for Lower RC Delay

Solution Overview

Problem

Current semiconductor devices face challenges in achieving high integration and improved performance, particularly in data storage and electrical conductivity, due to limitations in capacitive coupling and parasitic capacitance, which affect the RC delay and overall efficiency.

Innovation Solution

The semiconductor device incorporates alternating lower and upper conductive lines, single crystal semiconductor patterns, and intermediate conductive lines with shielding capabilities, along with data storage layers that include ferroelectric materials, to minimize capacitive coupling and enhance integration and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional conductive line structures are used, then device fabrication is simpler, but capacitive coupling and parasitic capacitance increase causing higher RC delay

Engineering Contradiction:

ImproveRC delayVSAvoidconductive line structure

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The conductive lines are segmented into alternating first and second conductive lines with different heights. The first conductive lines extend in a first direction at a first height, while the second conductive lines extend in a second direction at a second height. This segmentation reduces capacitive coupling between adjacent lines by separating them vertically and diagonally, thereby reducing parasitic capacitance and RC delay.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension to the conductive line structure by setting different heights for the first and second conductive lines. The first conductive lines are positioned at a first height level while the second conductive lines are positioned at a second height level, creating a three-dimensional interwoven pattern. This dimensional separation reduces the coupling capacitance between adjacent conductive lines compared to conventional planar structures.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If integration density is increased, then device functionality is enhanced, but parasitic capacitance and RC delay worsen

Engineering Contradiction:

Improveintegration densityVSAvoidRC delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The conductive lines are segmented into alternating first and second conductive lines with different heights. The first conductive lines extend in a first direction at a first height, while the second conductive lines extend in a second direction at a second height. This segmentation reduces capacitive coupling between adjacent lines by separating them vertically and diagonally, thereby reducing parasitic capacitance and RC delay.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the conductive line structure have different local qualities: the first conductive lines have a first local quality (first height, first direction) while the second conductive lines have a second local quality (second height, second direction). This local differentiation allows the structure to achieve high integration density while maintaining low parasitic capacitance in each local region through optimized spatial arrangement.

Inventive Principle:

Principle #3Local quality

3Area of stationary object

If conductive lines are placed closer together, then integration is improved, but capacitive coupling increases

Engineering Contradiction:

Improvedevice area utilizationVSAvoidcapacitive coupling

Core Design Contradiction:

Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The patent introduces a vertical dimension to the conductive line structure by setting different heights for the first and second conductive lines. The first conductive lines are positioned at a first height level while the second conductive lines are positioned at a second height level, creating a three-dimensional interwoven pattern. This dimensional separation reduces the coupling capacitance between adjacent conductive lines compared to conventional planar structures.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The conductive lines are segmented into alternating first and second conductive lines with different heights. The first conductive lines extend in a first direction at a first height, while the second conductive lines extend in a second direction at a second height. This segmentation reduces capacitive coupling between adjacent lines by separating them vertically and diagonally, thereby reducing parasitic capacitance and RC delay.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20230369214A1Semiconductor device including data storage layer

Publication Date: 2023.11.16 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device is provided. The semiconductor device includes: first lower conductive lines extending in a first direction and disposed at a first height level; first upper conductive lines extending in the first direction and vertically overlapping the first lower conductive lines at a second height level, higher than the first height level; single crystal semiconductor patterns disposed between the first lower conductive lines and the first upper conductive lines at a third height level; intermediate conductive lines extending in a second direction intersecting the first direction and passing between the single crystal semiconductor patterns, between the first height level and the second height level; and data storage layers including portions between the intermediate conductive lines and the single crystal semiconductor patterns.