Ferroelectric Thin-Film Storage Transistor for Endurance and Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing thin-film storage transistors face challenges in maintaining a wide programming window and high endurance due to interface trap formation and hot hole generation during programming and erase operations, leading to premature device failure.
Innovation Solution
The introduction of a charge-trapping layer with a conduction band offset less than the tunneling barrier and a barrier layer with a lower conduction band offset than the charge-trapping layer, combined with a thin tunnel dielectric layer, facilitates cool electron tunneling and reduces hot hole generation, enhancing endurance and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional tunnel dielectric layer and charge-trapping layer structure is used, then programming current density can be achieved, but interface trap formation and hot hole generation occur during programming and erase operations, leading to device degradation and reduced endurance
Solution Approach 1:
A barrier layer is introduced as an intermediary between the tunnel dielectric layer and the charge-trapping layer. This barrier layer has a conduction band offset that is lower than the charge-trapping layer but higher than the tunnel dielectric layer, creating a stepped energy profile that mediates electron transport. The barrier layer prevents direct interaction between high-energy electrons and the charge-trapping layer interface, thereby reducing interface trap formation and hot hole generation while maintaining programming current density.
Solution Approach 2:
The conduction band offsets of the tunnel dielectric layer, barrier layer, and charge-trapping layer are carefully engineered to create a specific energy profile. The tunnel dielectric layer has a high conduction band offset to prevent leakage, the barrier layer has an intermediate offset to control electron injection, and the charge-trapping layer has a lower offset to facilitate charge storage. This parameter optimization reduces hot hole generation and interface trap formation during programming and erase operations, improving device endurance.
2Productivity
If a thin tunnel dielectric layer is used to increase programming current density, then fast programming operations are achieved, but the tunneling barrier height is reduced, potentially increasing leakage current and reducing data retention
Solution Approach 1:
The energy barrier profile is made non-uniform through the introduction of the barrier layer with intermediate conduction band offset. The tunnel dielectric layer maintains a high conduction band offset to provide strong barrier properties and prevent leakage current, while the barrier layer and charge-trapping layer have progressively lower offsets to facilitate electron injection and storage. This local differentiation of barrier heights allows thin tunnel dielectric layers to achieve high programming current density without compromising data retention.
Solution Approach 2:
The gate stack is constructed as a composite structure with multiple dielectric layers (tunnel dielectric layer, barrier layer, and charge-trapping layer) having different conduction band offsets. This composite structure combines the advantages of thin tunnel dielectric layers (high programming current density) with the benefits of high barrier offsets (low leakage current and good data retention). The barrier layer acts as a transition zone that reconciles the conflicting requirements of fast programming and reliable data storage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high programming current density and fast operations while maintaining a wide programming window and reducing device degradation, suitable for quasi-volatile storage transistors in 3-dimensional memory arrays.
Implementation Method 1
electrons direct tunnel into the charge-trapping layer
Implementation Method 2
FeFETs with a ferroelectric storage layer
Data Source
AI summary
By harnessing the ferroelectric phases in the charge storage material of thin-film storage transistors of a 3-dimensional array of NOR memory strings, the storage transistors are adapted to operate as ferroelectric field-effect transistors (“FeFETs”), thereby providing a very high-speed, high-density memory array.