Ferroelectric Threshold Gate with Adaptive Logic Switching
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Solution Overview
Problem
Existing multi-input logic gates consume high power due to the large number of transistors and interconnects, posing a challenge for reducing power consumption in electronic devices.
Innovation Solution
A capacitive input circuit with a configurable threshold is developed, using ferroelectric material capacitors and pull-up/pull-down devices to adjust the switching threshold, allowing the circuit to perform various logic functions by sequencing the turn-on/off of these devices during a reset phase, enabling the circuit to operate as different types of gates such as NAND/AND, OR/NOR, or majority/minority gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If traditional multi-input logic gates are implemented using multiple transistors and interconnects, then logic functionality is achieved, but power consumption increases significantly
Solution Approach 1:
The patent implements a universal capacitive logic gate that can perform multiple logic functions (AND, OR, NAND, NOR, majority, minority) using the same physical circuit structure. By configuring the capacitive inputs and control signals differently, the same hardware achieves different logical operations, eliminating the need for separate transistor networks for each gate type and significantly reducing power consumption.
Solution Approach 2:
The patent merges multiple logic gate functions into a single capacitive circuit structure. Instead of having separate transistor-based AND, OR, NAND, and NOR gates, the invention combines them into one unified capacitive logic element that can be dynamically reconfigured to perform any of these functions through control signal sequencing during reset phases.
2Device complexity
If the same circuit is configured to perform multiple logic functions, then device complexity is reduced, but the ability to adapt to different logic operations may be compromised
Solution Approach 1:
The patent employs dynamic reconfiguration of the capacitive logic gate through controlled charging and discharging sequences during reset phases. By dynamically adjusting which capacitive inputs are charged to specific voltage levels and in what sequence, the circuit adapts its transfer characteristics to implement different logic functions, making the system versatile despite having a fixed physical structure.
Solution Approach 2:
The patent changes the electrical parameters (voltage levels, charging sequences, control signal timing) of the capacitive inputs to achieve different logic functions. By modifying parameters such as the voltage applied to each capacitive input and the timing of control signals during reset phases, the same hardware structure produces different logical outputs corresponding to AND, OR, NAND, NOR, majority, or minority operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces power consumption by allowing the same circuit to perform multiple logic functions with minimal additional transistors, achieving low leakage and reduced static power consumption, making it suitable for advanced process technology nodes.
Implementation Method 1
using ferroelectric material capacitors
Data Source
AI summary
An apparatus and configuring scheme where a ferroelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the ferroelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and pull-down devices are turned on in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.