Ferroelectric Transistor Domain Wall Modulation for Multi-Level Memory
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Solution Overview
Problem
Conventional memory devices are inefficient for modern applications such as deep-learning, image and video processing, and neuromorphic tasks, as they can only store binary digital values, limiting their capacity and power efficiency.
Innovation Solution
The use of ferroelectric transistors with a domain wall in a ferroelectric-oxide layer to store multiple resistance states, allowing for the representation of real numbers and enhancing storage density and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory devices are used to store binary digital values, then the device structure is simple, but the storage density and power efficiency are insufficient for modern applications
Solution Approach 1:
The patent changes the physical parameter of resistance from binary (two states) to multi-level (multiple states) by controlling the domain wall position in the ferroelectric-oxide layer. This allows a single memory cell to store multiple bits of information, increasing storage density without proportionally increasing device complexity
Solution Approach 2:
The patent uses a composite structure combining ferroelectric-oxide layer with metal electrodes (top electrode and bottom electrode) to create a ferroelectric transistor. This composite material system enables the domain wall formation and position-dependent resistance modulation that achieves high-density storage
2Use of energy by moving object
If conventional binary memory storage is used, then the device operation is simple, but power consumption is high and performance is limited for neuromorphic applications
Solution Approach 1:
The patent utilizes continuous parameter variation (domain wall position) to represent analog values, enabling efficient storage of weights in neural networks. This reduces the need for frequent memory updates and lowers power consumption compared to binary memory systems performing the same neuromorphic tasks
Solution Approach 2:
The ferroelectric material inherently maintains the domain wall position and associated resistance state without requiring continuous power supply. This self-retaining property reduces static power consumption while maintaining the stored information for neural network operations
3Quantity of substance
If multiple resistance states are stored using ferroelectric transistors, then storage density and power efficiency improve, but the device structure and operation become more complex
Solution Approach 1:
The ferroelectric-oxide layer serves multiple functions: it acts as the gate dielectric, the medium for domain wall formation, and the element that modulates channel resistance. This multi-functionality reduces the need for additional separate components, managing device complexity while achieving high storage density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-density multi-level memory devices that consume lower power and improve performance in applications like deep neural networks, matching human-level tasks in language processing and image recognition.
Implementation Method 1
a gate stack above the channel layer, where the gate stack includes a ferroelectric-oxide layer above the channel layer and in contact with the channel layer
Implementation Method 2
A domain wall may be generated within the ferroelectric-oxide layer by a programming voltage pulse applied to the top electrode. The domain wall may be positioned in various locations within the ferroelectric-oxide layer.
Implementation Method 3
A resistance between a source electrode and a drain electrode of the ferroelectric transistor is modulated in a range between a first resistance value and a second resistance value, dependent on the position of the domain wall within the ferroelectric-oxide layer of the gate stack
Data Source
AI summary
Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.