Ferroelectric Transistor Assembly for Faster Programming
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Solution Overview
Problem
Conventional ferroelectric transistors face challenges in rapid programming due to floating-body effects, which hinder the replenishment of carriers and reduce programming speed, making it difficult to achieve scalable and efficient memory array performance.
Innovation Solution
The design incorporates a ferroelectric transistor structure with a second conductive gate coupled to driver circuitry and a conductive structure to drain excess carriers from the channel region, alleviating floating-body effects and enhancing carrier replenishment, while the ferroelectric material is configured to extend vertically to manage grain size variations across the array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional ferroelectric transistor configurations are used, then device simplicity is maintained, but programming speed is reduced due to floating-body effects
Solution Approach 1:
The transistor body region is segmented into a first body region and a second body region, with the first body region being doped to provide carriers and the second body region remaining lightly-doped or undoped for memory storage. This segmentation allows the doped region to supply carriers rapidly during programming operations, overcoming the floating-body effect limitation while maintaining the functional integrity of the memory structure.
Solution Approach 2:
A conductive structure is introduced as an intermediary element that couples the first body region to a carrier source. This conductive structure acts as a mediator that enables rapid carrier replenishment in the lightly-doped body region during programming operations, effectively resolving the carrier depletion issue without requiring complete restructuring of the transistor architecture.
2Productivity
If body regions are isolated to maintain transistor function, then device operation is simplified, but carrier replenishment rate is reduced
Solution Approach 1:
Different regions of the transistor body are assigned different doping qualities: the first body region is heavily doped to serve as a carrier reservoir, while the second body region is lightly-doped or undoped to maintain the memory storage function and reduce floating-body effects. This local differentiation of material properties enables simultaneous optimization of carrier supply and memory performance.
Solution Approach 2:
The conductive structure serves as an intermediary pathway that connects the carrier-rich first body region to the carrier-needy second body region. This intermediary connection enables controlled carrier flow from the doped region to the lightly-doped region, accelerating carrier replenishment while maintaining the functional separation needed for memory operation.
3Reliability
If rapid carrier replenishment is achieved, then programming speed improves, but device structure becomes more complex
Solution Approach 1:
The body region is divided into functionally distinct segments: a first body region optimized for carrier supply through doping, and a second body region optimized for memory storage with light or no doping. This segmentation enables reliable rapid programming by ensuring adequate carrier availability while maintaining the structural simplicity needed for manufacturability.
Solution Approach 2:
The first body region serves multiple functions: it acts as both the structural foundation for the transistor and a carrier reservoir that replenishes carriers during programming operations. This multi-functionality reduces the need for additional dedicated structures, thereby limiting the increase in device complexity while achieving reliable rapid programming.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables faster programming and improved scalability of ferroelectric transistors, reducing variations in performance characteristics across the memory array, thus enhancing the suitability and efficiency of the memory array for intended applications.
Implementation Method 1
the different polarization modes may be characterized by, for example, different threshold voltages (VT) or by different channel conductivities for a selected operating voltage. The ferroelectric polarization mode of a FeFET may remain in the absence of power
Implementation Method 2
In operation, an electric field across the ferroelectric material is used to switch the ferroelectric material from one polarization mode to another
Implementation Method 3
conductive structures that drain excess carriers from the channel regions to alleviate floating-body effects, enhancing carrier replenishment and programming speed
Data Source
AI summary
Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.